1) high-voltage CMOS devices
高压CMOS器件
1.
As the development of CMOS technology,high-voltage CMOS devices and low-voltage circuits can be integrated in the same chip,so the cost of the system can be reduced and the reliability of the circuit can be improved.
8μm标准CMOS工艺条件对于高压CMOS器件进行了工艺和器件模拟。
2) CMOS devices
CMOS器件
1.
This paper presents the string elements for Single Event Latchup,and discusses the major characters and test method for Single Event Latchup of CMOS devices.
介绍了单粒子锁定现象的触发原理,探讨了针对典型CMOS器件SEL现象的主要特征和测试方法,并开展了几种CMOS器件的单粒子锁定试验研究。
2.
The partially depleted SOI CMOS devices and circuits with channel length of 0.
8μm部分耗尽绝缘体上硅(PDSOI)CMOS器件和电路,开发出成套的0。
3.
12μm gate length CMOS devices are fabricated.
在此基础上 ,采用Si3 N4/SiO2 stack栅介质制备出性能优良的栅长为 0 12 μm的CMOS器件 ,器件很好地抑制了短沟道效应 。
3) CMOS device
CMOS器件
1.
Comparison on effects of CMOS devices irradiated by gamma and X ray;
CMOS器件X射线与γ射线辐照效应比较
2.
Deep sub-micron CMOS device modeling and BSIM models;
深亚微米CMOS器件建模与BSIM模型
3.
In studying latchup window phenomena in bulk-Si CMOS devices,a new method for prevention of latchup has been discovered,which is called pseudo-latchup path method.
在研究体硅CMOS器件的闭锁窗口现象时,发现了一种新的抗闭锁方法———伪闭锁路径法。
4) post CMOS
后CMOS器件
1.
s:Several new devices which are the candidates of post CMOS devices possibly were introduced,including resonant tunneling transistors,single,electron transistors,CNTFETs,molecular devices and spin transistors.
介绍了几种后CMOS器件可能的候选器件:谐振隧道器件、单电子晶体管、碳纳米管晶体管、分子器件和自旋晶体管。
6) High-voltage CMOS process
高压CMOS流程
补充资料：高压线走廊（高压架空线路走廊）
在计算导线最大风偏和安全距离情况下，35kV及以上高压架空电力线路两边导线向外侧延伸一定距离所形成的两条平行线之间的专用通道。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条