2) SDH equipment clock
SDH设备时钟(SEC)
3) clock event device
时钟事件设备
4) clock design
时钟设计
1.
PECL signal makes this logic suitable for high-speed ADC clock design.
PECL(正电压射极耦合逻辑)信号作为一种适合高速逻辑互联的电平标准,越来越多地应用在高速A/D转换器的时钟设计中。
2.
This article discusses five different clock design schemes in FPGA design,analyzes the advantages and disadvantages of these different schemes as well as some critical points in their design.
探讨了FPGA设计过程中5个不同的时钟设计方案,对这些不同方案的优点、缺点和在设计中需要注意的问题进行了分析,并提出了一些合理建议。
3.
Six clock design measures for the field programmable gate array(FPGA) are described in this paper which preset a credible clock design according to the setup time,hold time and synchronous principle.
对于现场可编程门阵列(FPGA)常见的6种时钟设计,根据建立时间和保持时间的要求,按照同步设计原则,分别给出可靠的时钟设计方案。
6) one clock design
单时钟设计
补充资料：设备
满足生产或生活上所需的成套建筑、器物等：设备完善｜实验室将陆续增添种种设备。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条