Researches are focused on rounding methods for high-speed floating-point multipliers in the paper,and a kind of fast rounding method based on the prediction and selection is presented.

A double-precision Floating-point multiplier with fast rounding method is presented in the paper.

Parameterized IP of floating point multiplier design method based on Verilog HDL is discussed in this paper,and three kinds of parameters are picked out.

Using Verilog HDL,a design of 32 b single precision floating point multiplier based on FPGA is presented.

Research on 32 Bit High-Speed Floating-Point Multiplier Design;

A high-speed floating-point multiplier is presented in this paper.

Multiple-input floating-point multiplier is usually composed of several double-input floating-point multipliers,and it s inevitable to increase logic resource and processing latency,which makes it harder and harder to meet the requirement of high-speed digital signal processing.

Based on the analysis of the muiltiplicative structure of Koszul algebras given by Buchweitz et al,a sufficient and necessary condition for the multiplicative structure of Hochschild cohomology rings of Koszul algebras to be essentially the jux- taposition of parallel paths is obtained.

Moreover,in order to avoid overflowing,it also uses block-floating-piont structure that can save many hardware resources.