1.
Research on 32 Bit High-Speed Floating-Point Multiplier Design;
32位高速浮点乘法器设计技术研究
2.
The Design of High Speed Pipeline Floating Point Multiplier Based on FPGA
基于FPGA的高速流水线浮点乘法器设计
3.
Design and Implementation of Single-precision Floating Point Multiplier Based on Verilog
基于VeriIog的单精度浮点数乘法器的设计与实现
4.
floating-point adder
浮点加法器，浮点加
5.
The Design of Floating-Point Multiply-Add Fused Units in General Purpose Processors;
高性能通用处理器中浮点乘加部件的设计
6.
24 Fixed-point DSP Parallel Multiplier Design;
基于24位定点DSP的并行乘法器的设计
7.
Implementation of 20×18 bit Sign Fix Point Multiplier Based on FPGA
20×18位符号定点乘法器的FPGA实现
8.
In a floating-point representation, the numeral that is multiplied by the exponentiated implicit floating-point base to determine the real number represented.
浮点表示法中的一个数字，该数字乘上隐式的浮点底数的幂就决定了所表示的实数。
9.
The Design of Fast 1 s-complement Adder Base on IEEE754 Standard Floating-point Number;
基于IEEE754浮点数的快速反码加法器设计
10.
The realization of the fast adder-subtracter for the 23 bit’s floating point numbers by VHDL
用VHDL实现的23位快速浮点数加减法器
11.
Design of the Floating Point Adder and Research of Its Bist
FPU中浮点加法器的设计及其内建自测试的研究
12.
cursor type IFP
游标型瞬时浮点放大器
13.
Digit-serial binary field multiplier based on Mastrovito multiplication
基于Mastrovito乘法的字串行特征二域乘法器
14.
The Research and Implementation of Double Data-path Fused Floating Point Multiply-Add Supporting Parrall Multiply;
支持并行整数乘的双通路浮点融合乘加结构的研究与实现
15.
Research and Realization of a 128-Bit Multiply-Add-Fused Unit
一种128位高精度浮点乘加部件的研究与实现
16.
Analysis of Lagrange Multiplication;
对Lagrange乘数法的两点浅析
17.
quarter-square multiplier
四分之一平方乘法器
18.
analog multiplier hybrids
模拟乘法器混合微电路