Improved delay estimation method for RLC interconnects;

Modeling of RF Coupled Interconnects on Lossy Silicon Substrates;

Exploiting clock circuit dynamical optimization using RLC interconnect model;

Finally,a method of building the Spice model with high-frequency interconnection line in the substrate is proposed,thus providing a foundation for coordination design of chip package.

In this case, interconnection lines between the chips in the Multi-Chip Module (MCM) or Printed Circuit Board (PCB) have become the important factors of the signal integrity and entire system performance.

Design and Implementation of 3D Interconnections Capacitance Extraction;

This paper introduced copper as substitute for aluminum as the metal interconnection with its low resistance rate and high resist-electron migration ability, briefed on the preparation techniques of Cu, and then discussed the new disfigurement and its solution such as groove disfigurement, bubble disfigurement and metal loosing disfigurement.

Considering the serious RC network effects of interconnections in very high speed digital ICs, the parasitic parameters of the interconnections with TSMC 0.

In order to study the failure of IC devices induced by the stress in VLSI metal interconnect, In-situ observation of the stress changes of VLSI Al interconnect was studied under the electromigration and thermal conditions by using a synchrotron radiation x-ray diffraction technique.

On-chip Inductance Modeling of VLSI Interconnects Based on Neural Networks;

Modeling of interconnects and delay analysis in the presence of Random VLSI process variations

To extract the 2-D capacitance distributed parameters of interconnects accurately and fast,a measured equation of invariance method is used to calculate the electric field of interconnects,and the effect of the aberration of conductor sizes on the parasitic extraction is discussed.