1) TimeQuest timing constrain
TimeQuest时序约束
2) TimeQuest timing analyzer
TimeQuest时序分析器
1.
All signals of Synchronous Dynamic Random Access Memory(SDRAM) are synchronized with clock signal setup and hold rules must be met otherwise would lead to data errors This paper describes the basic methods using TimeQuest timing analyzer for static timing analysis(STA) in designing SDRAM controller on FPGA.
本文叙述了在采用FPGA设计SDRAM控制器时,利用TimeQuest时序分析器(TQ)进行静态时序分析(STA)的基本方法和流程,并通过实验说明了STA的作用。
3) timing constraints
时序约束
1.
This paper introduces the basic principle of Static Timing Analysis(STA) for verifying FPGA design and some timing constraints related to STA.
介绍了采用STA(静态时序分析)对FPGA(现场可编程门阵列)设计进行时序验证的基本原理,并介绍了几种与STA相关联的时序约束。
4) timing constraint
时序约束
1.
This paper takes the residue number system as example, result in sub-module with different timing constraint at the architecture level.
并以剩余数系统为例进行仿真说明,在体系结构层得到具有不同时序约束的子模块,在电路层根据不同的路径长度分成两种不同的供电电压,达到降低功耗的目的。
2.
The basic timing constraints concept in ASIC design has been introduced in this paper, then with the ASIC design of VC12-VC4 E1 mapper in SDH system, the related timing constraints have been demonstrated in detail.
文中介绍了设计中所需考虑的各种时序约束 ,并以同步数字系列 (SDH)传输系统中 8路VC12 VC4E1映射电路设计为例 ,详细说明了设计中所采用的时序约束 ,并通过静态时序分析 (STA)方法使电路时序收敛得到了很好的验证。
5) temporal constraint
时序约束
1.
UML-statecharts based verification of consistency of temporal constraints of the workflow;
基于UML状态图的工作流时序约束一致性研究
2.
Temporal Constraint Based Specification of Component Interaction Protocols;
基于时序约束的构件交互协议描述
3.
This paper introduces how to use composition template under temporal constraint in detail.
该文重点介绍了时序约束下如何利用组合模板进行业务级的服务组合。
6) sequential constraint
时序约束
1.
It derives race variants set from synchronization events which have no sequential constraints,and avoids or reduces the generating of infeasible race variants.
为了提高在Java程序可达性测试中的同步序列生成效率,提出了一个新算法从无时序约束关系的同步事件派生竞争变形体集,避免或减少了不可行的竞争变形体的生成。
补充资料：时序女神
时序女神(horae)：宙斯和忒弥斯诸女，
欧诺弥亚(eunomia）秩序女神
狄刻(dike)公正女神
厄瑞涅(eirene）和平女神.
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条