1) grain-boundary barrier model
晶界势垒模型
1.
The carrier transport characteristics of the InN thin films have been explained successfully on the basis of a grain-boundary barrier model, where the accumulation of holes at the grain boundaries has been found to play a key role.
在晶界势垒模型的基础上 ,发现InN薄膜的电导特性取决于材料内部的晶界势垒高度 ,载流子输运特性是由于空穴在晶界处的积累决定的 。
2) grain boundary barrier
晶界势垒
1.
Study on the UV photo-sensitive characteristic and grain boundary barrier of ZnO thin films
ZnO薄膜紫外光敏特性及晶界势垒的研究
2.
The low B-value of the grains and insignificant grain boundary barrier give a good linear resistance-temperature characteristic of the composite within a temperature range of -20￣250℃.
由于复合材料的晶粒具有极小的Ｂ值而晶界势垒也极小，使得该复合材料的电阻－温度特性呈现出良好的线性特征。
3.
A new interpretation for the origin the grain boundary barrier is oxide semiconductorceramics is proposed,It is suggested by the authors that the barrier originates from the dif-fusion of excess oxygen in grain boundaries during sintering.
提出了一个关于氧化物半导瓷晶界势垒起源的新观点，认为晶界势垒起源于烧结过程中外界氧在晶界中的扩散，与材料的结构、化学缺陷、掺杂、外界气氛、烧结工艺、组成状态等有密切关系，并用此理论解释了许多实验现象。
3) grain-boundary barrier
晶界势垒
1.
It is believed that the grain-boundary barrier of the thin.
结果表明,适当的掺杂量可以改善CdTe薄膜的结晶性能,降低晶界势垒高度,提高其导电性能。
2.
The results show that the decomposition accompanying with oxidation is useful forincreasing the surface state density and the height of grain-boundary barrier, and therefore improves the nonlinear property of TiO_2 capacitor.
结果发现，在晶界处发生的热分解氧化反应能增加界面态密度，提高晶界势垒高度，从而改善ＴｉＯ２电容压敏电阻器的非线性性能。
4) potential barrier mode
势垒模型
1.
The maximum potential barrier height was deduced from experimental data according to the modified potential barrier model.
在不同的施主杂质Nb2O5含量下,对BaTiO3半导陶瓷样品测量了电流—电压关系,发现结果不遵循经典的海旺(Heywang)模型,而与从修正的势垒模型出发得到的结果符合较好。
5) barrier height at grain boundaries
晶界势垒高度
1.
Through measuring the barrier height at grain boundaries, it is found that the sharp decrease of ZnO grain size mainly contributes to the significant increase of voltage gradient.
晶界势垒高度揭示,ZnO晶粒尺寸的迅速减小是压敏电位梯度急剧增高的主要原因。
6) square barrier model
方势垒模型
1.
In this paper, an object of study in EDN, the square barrier model is set up, the mechanism of electron tunnel effect is discussed in EDN, and the explanation of Bohr quantum theory is given on the spark phenomenon in EDN.
以电火花线切割加工为研究对象,通过建立方势垒模型,阐述了电火花加工中的电子隧道效应机理,并对放电加工中出现的火花现象给出了Bohr的量子论解释。
补充资料：pn结势垒（barrierofp-njunction）
pn结势垒（barrierofp-njunction）
pn结的空间电荷区中，存在由n边指向p边的自建电场。因此，自然形成n区高于p区的电势差Vd。相应的电子势能之差即能带的弯曲量qVd称为pn结的势垒高度。pn结的p区和n区的多数载流子运动时必须越过势垒才能到达对方区域，载流子的能量低于势垒高度，就被势垒阻挡而不能前进，这个垫垒叫做pn结势垒。pn结的势垒高度与两边半导体中的杂质浓度及其分布、温度以及半导体材料的禁带宽度Eg有关。除pn结势垒外，还有金属与半导体接触的接触势垒（肖特基势垒）、半导体表面形成的表面势垒等。势垒高度受外加电场的影响，当外加电场削弱势垒区中电场时，势垒降低，载流子容易通过；外加电场加强势垒区的电场时，势垒高度升高，载流子不易通过。利用pn结势垒这一特性可制成整流、检波等多种半导体器件。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条