1) design for testability
可测性设计
1.
Design For Testability of Mixed Analog and digital Integrated Circuits;
数模混合集成电路的可测性设计
2.
Design for Testability of a Novel High-Speed DCT in VLSI;
高速离散余弦变换VLSI实现的可测性设计
3.
A scan-based design for testability scheme is proposed for built-in self-test of pipelined FFT processor utilizing its highly regular architecture.
该方案充分利用FFT结构上的规则性,采用扫描的可测性设计,不需要对处理器内部基本功能单元作任何更改,且测试序列生成和响应压缩都可通过对已有功能模块如累加器的复用来完成。
2) DFT
可测性设计
1.
DFT Strategy of SOC;
SOC的可测性设计策略
2.
DFT analyses of PCB based on boundary-scan technology;
基于边界扫描技术的电路板可测性设计分析
3.
DFT of embeded memory in SoC;
嵌入式存储器在SoC中的可测性设计
3) Design for test
可测性设计
1.
We hope that the research is a good guide for the study on design optimization,design for test and verification.
基于ASIC设计流程,讨论了当前ASIC设计中逻辑综合、易测性、低功耗等一些典型问题,并以工艺独立阶段和工艺映射阶段中ASIC综合需要解决的问题为研究重点,结合实例分析了其中的关键环节,以期作为高性能ASIC设计优化、可测性设计、设计验证等方向分析研究的前期工作。
2.
This paper studies the design for test of PCB by using the boundary scan technique, gives out a concrete implementing method and presents the realization of the measurability designs of some circuit boards.
运用边界扫描技术,对PCB可测性设计进行了研究,给出了具体实现方法,并实现几种电路板的可测性设计。
3.
The design for test of PCB based on the boundary scan technique is researched from designed method,optimization strategy,realization technique and so on.
阐述了边界扫描技术的基本原理,从设计方法、优化策略及实现技术等方面,对基于边界扫描技术的PCB可测性设计进行了研究,并给出了具体的实现方法;以对某海军导弹通用测试系统中的数据采集电路板进行改进为例,实现了该电路板的可测性设计;经验证,该方法有效地缩短了数据采集电路板的开发周期,降低了其维修测试费用,因而将具有更为广泛的应用前景。
4) design-for-testability
可测性设计
1.
Arithmetic test and design-for-testability for FFT processor;
FFT处理器的算术测试与可测性设计
2.
Structural design-for-testability of accumulation-based testing for DSP data path
DSP数据通路基于累加器测试的结构可测性设计
3.
Based on arithmetic additive generator, we present an universal design-for-testability and test strategy for infinite impulse response (IIR) filter.
基于加法器测试生成,提出了无限脉冲响应(IIR)滤波器的一种通用可测性设计、测试方案。
5) testability design
可测性设计
1.
Finally this paper demonstrates the operating process and testing results with an example of testability design f.
同时,以一个逻辑分析模件的可测性设计再开发过程为例说明系统的使用方法,展现了虚拟仪器的有效性和实用性。
2.
Testable topological structure and testable topological condition for branching diagnostic method are analyzed,testability analysis and testability design are presented.
针对支路诊断法分析了电路的可测拓扑结构和可测拓扑条件,提出了可测性分析和可测性设计方法。
3.
The testability measurement is the basic theory of testability design.
对具体数字电路的设计改进实例表明,该方法在电路可测性设计中有效可行。
6) Design for testability
可测试性设计
1.
Because of the high integration characteristic of resonant tunneling diode (RTD) circuits, design for testability is significantly important to simplify the RTD circuits testing.
针对共振隧穿二极管(RTD)电路由于具有超高集成度特点所带来的电路测试困难,在故障分析与故障模型的基础上提出了RTD电路的可测试性设计方案。
2.
Boundary Scan Technique (BST) is a new and effective way of test and design for testability for VLSI circuits.
1边界扫描机制是一种新型的VLSI电路测试及可测试性设计的有效方法,为了高效地应用边界扫描机制对电路系统进行测试,必须对其所涉及的理论方法进行深入探讨。
3.
The idea of test and design for testability is discussed, the challenges of test and design for testability are analyzed, then the test and design for testability in SOC design are discussed.
CMOS器件进入超深亚微米阶段,集成电路(IC)继续向高集成度、高速度、低功耗发展,使得IC在测试和可测试性设计上都面临新的挑战。
补充资料：连续性与非连续性(见间断性与不间断性)
连续性与非连续性(见间断性与不间断性)
continuity and discontinuity
11an父ux泊g四f“山。麻以角g、.连续性与非连续性(c。nt，n琳t:nuity一)_见间断性与不间断性。and diseo红ti-
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条