1) ADPLL(All Digital Phase Locked Loop)
ADPLL(全数字锁相环)
2) all digital phase-locked loop(ADPLL)
全数字锁相环ADPLL
3) All-digital Phase Locked Loop(ADPLL)
全数字式锁相环(ADPLL)
4) ADPLL
全数字锁相环
1.
Design of An Improved ADPLL Base on FPGA;
基于FPGA的全数字锁相环性能改进的设计
2.
The design of self-sampling PI control all digital phase-locked loop(ADPLL) is implemented on the FPGA chip.
分析了一种基于现场可编程逻辑器件(FPGA)的谐振型逆变器控制电路,在FPGA芯片上实现了自采样比例积分(PI)控制全数字锁相环(ADPLL)的设计。
3.
A mathematical model is developed to derive the related parameters of the ADPLL.
提出了一种特殊的计数器,并基于此建立起新型的、具有极窄带宽的全数字锁相环电路,该电路用于SDH系统中E1支路信号时钟的恢复。
5) all-digitized phase lock loop
全数字锁相环路
1.
Through VHDL hardware description language and increasing state detection of function module in PLL,the detection of working state of PLL(out of lock or lockage)can be realized in the chip of all-digitized phase lock loop realized by FPGA programmable technology.
在采用FPGA可编程技术实现的全数字锁相环路芯片中,通过使用VHDL硬件描述语言增加锁相环状态检测功能模块,能实现对锁相环工作状态(失锁或锁定)的检测。
6) all digital phase-locked loop
全数字锁相环
1.
A fast all digital phase-locked loop with automatic modulus control is presented.
提出了一种具有自动变模控制的快速全数字锁相环。
2.
With the flying development of large scale and super high speed integrated circuit, the integration of digital system becomes higher and higher, and the logic speed becomes faster and faster, which makes the application of all digital phase-locked loop in every domain of digital communication, control project and wireless electronics more and more extensive.
随着大规模、超高速集成电路的飞速发展,数字系统的集成度越来越高,运算速度越来越快,这使得全数字锁相环在数字通信、控制工程及无线电电子学的各个领域中的应用也越来越广泛。
3.
In this paper,a method that realizes all digital phase-locked loop by Verilog hardware description language is presented.
文章提出了一种运用Verilog硬件描述语言实现全数字锁相环的方法。
补充资料：[3-(aminosulfonyl)-4-chloro-N-(2.3-dihydro-2-methyl-1H-indol-1-yl)benzamide]
分子式：C16H16ClN3O3S
分子量：365.5
CAS号：26807-65-8
性质：暂无
制备方法：暂无
用途：用于轻、中度原发性高血压。
分子量：365.5
CAS号：26807-65-8
性质：暂无
制备方法：暂无
用途：用于轻、中度原发性高血压。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条