Three different sampling clock frequency offset and residual frequency offset estimation methods were developed to improve their estimation accuracy in internet protocol-orthogonal frequency division multiple access(IP-OFDMA)system,and the characteristics of the pilot structure in IP-OFDMA system was considered.

The model between a switch under tested(SUT) and a Smartbits card is presented and used for two interconnecting switches,this paper presents that clock frequency error(CFE) between a SUT and a Smartbits card is a leading factor of forwarding delay in an ethernet switch.

A yield driven clock skew scheduling algorithm is proposed in presence of process variations.

This paper presents an effective approach for clock skew scheduling that can reduce the center error square and assign slacks incrementally.

In multi-FPGA designs, the delay of clock transfer causes a huge clock skew between FPGAs and therefore undermines the system performance.

It can improve the weakness of the primary iterative ML algorithm in the estimation of timing and frequency offset in AWGN noise channel and establish accurate synchronization in the multi-path fading channel.

This paper introduces A/D Converter ICL7135 Series Collection in Single-chip Microcomputer Voltage Meter,interface circuit and clock frequency of AT89C51 and ICL7135.

The relations among the error of frequency measurement, measure time, reference clock frequency and the measured signal frequency, are also deduced.

Dynamic voltage scaling (DVS) technique is an effective way to reduce processor energy consumption through changing the processor’s supply voltage and clock frequency at the runtime.