1.
A personal computer with a 100-megahertz clock then executes 100 million stages per second.
一台时钟频率为100兆赫的个人电脑每秒能执行一亿次运算。
2.
The number of stages completed each second is given by the so-called clock rate.
每秒所完成的步骤数目用所谓的时钟频率来表示。
3.
We can expect pipelines having even more stages and higher clock rates.
我们期待微处理器流水线操作，有更多的步骤和更高的时钟频率。
4.
One 1995 microprocessor uses this deeper pipeline to achieve a 300-megahertz clock rate.
一台1995年生产的微处理器用这种更先进的流水线操作可达到300兆赫的时钟频率。
5.
This article mainly addresses the maintenance period of clock frequency of SPC exchanges in China's telecommunication network.
本文主要讨论我国电信网中程控交换局时钟频率维护周期的确定问题。
6.
The high clock frequency requirements will have to be weighed against the need for tighter design criteria that ensure high noise immunity.
高时钟频率的要求比高抗扰度的要求更为重要，因为高抗扰度可通过精心设计予以保证。
7.
frequency master control instrument for synchronous clocks or time switches
频率主控仪表,用于同步时钟或时开关
8.
For very high frequency clocks, a surface acoustic wave (SAW) oscillator is preferable.
对于非常高的频率时钟，用声表面波振荡器更好。
9.
TIME: The scanner will halt on a signal it encounters, and will hold five seconds.
时间：扫描将停在发现的一个信号频率上5秒钟。
10.
The clock used should be free from significant phase or frequency jitter.
应用的时钟应没有重大的周期或频率的跳动。
11.
Frequency Measurement Method of Synchronization Clock Calibration in Distributed Testing System
分布式测试系统同步时钟校准的频率测量方法
12.
A High Precision Clock Oscillator Based on Frequency-to-Voltage Converter
一种基于频率-电压变换器的高精度时钟振荡器
13.
Analyses of Main Error Sources on Time-Domain Frequency Stability for Atomic Clocks of Navigation Satellites
导航卫星原子钟时域频率稳定性影响因素分析
14.
that the rate of a clock moving through space will decrease as its speed increases;
在空间移动的时钟钟摆频率会随着运动速度的增加而减慢；
15.
This is the basis for the well-known cesium clock, presently the standard of frequency and time.
这就是众所周知的铯原子钟的基础，它是目前的频率和时间基准。
16.
Each bit can flip 1020 times per second, equivalent to a clock speed of 100 giga-gigahertz.
每个位元每秒可翻转1020次，大约比振?频率10亿赫兹的时钟快1000亿倍。
17.
5-Gb/s multiplexer with integrated clock extraction and frequency multiplication
具有时钟提取及倍频功能的5Gb/s全速率复接器设计
18.
The Realization of Division and Multichannel Output of High-Frequency Clock Using the FPGA;
用FPGA实现高频时钟的分频和多路输出