1) carry truncation
进位截断
1.
The results show that the carry elimination mechanism has shorter delay,fewer gates and lower power consumption than carry truncation mechanism.
基于门延迟模型对加法器原理及性能进行了分析,设计了进位截断和进位消除两种子字并行控制机制。
2) phase truncation
相位截断
1.
Amplitude-quantization spurs in direct digital frequency synthesizers in absence of phase truncation;
无相位截断情况下DDS的幅度量化杂散特性分析
2.
Emulational analysis of the spectrum characteristic caused by the phase truncation in direct digital frequency synthesizer;
DDS频率合成器相位截断误差频谱特性仿真分析
3.
The output signal background spurious brought about by phase truncation and digital amplitude are explained from the angle of the theory of signal and system,and in the end the effects of D/A s none ideal characteristics and the clock s phase noise are expounded.
首先介绍了直接数字合成(DDS)技术的基本原理和理想情况下DDS的输出信号频谱结构,然后分析了工程实际中DDS的误差信号来源,从信号与系统理论的角度解释了相位截断和幅度量化引起的DDS输出信号频谱的杂散,并在最后对D/A的非理想特性和参考时钟相位噪声的影响作了简要的说明。
3) judge carry
进位判断
4) air inlet shutoff
进气截[关]断装置
5) phase truncation error
相位截断误差
1.
The spectrum characteristics of the phase truncation error and amplitude quantization error are analyzed by the method of Fourier series.
介绍了直接数字频率合成技术以及分析其杂散误差,对相位截断误差和幅度量化误差进行了傅立叶级数分析研究。
2.
This paper introduces the theory of the phase-locked loop (PLL) and the direct digital synthesis (DDS) , a method to improve the precision of DDS and reduce its phase truncation error is also given.
介绍了锁相环(PLL)技术和直接数字式频率合成(DDS)技术的基本工作原理,给出了一种提高DDS输出频率精度及减小其相位截断误差的方法。
3.
This paper analyzes the processing of direct digital frequency Synthesizer and get the relation of phase truncation error and frequency control truncation word.
通过分析直接数字频率合成器的工作过程，利用相位截断误差与频率控制截断字的关系，给出了频率控制截断字对杂散的分布及幅度的影响，提出了利用频率控制截断字计算杂散的方法，从而减小了频率混叠对计算杂散的影响。
6) Phase truncation effect
相位截断效应
补充资料：进位
加法中每位数等于基数时向前一位数进一，例如在十进位的算法中，个位满十，在十位中加一，百位满十，在千位中加一。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条