Based on the in-depth research of FT-C55LP’s characteristics of instruction sets and instruction parallel, I have a comprehensive and detailed analysis of the instruction sets of FT-C55LP, and put forward a design plan of decoding controlling unit, which is divided into three modules: parallel instruction splitting, single instruction decoding, and decoded signal incorporating.

The hierarchical memory management of BF535 is analyzed, and the memory in different region is described, According to the L1 and L2 RAM of the DSP, parallel instruction and FFT operation is evaluated.

In order to fully utilize the instruction level parallelism of the recent VLIW DSP processors, DSP programs have to be optimized by software pipelining.

Instruction scheduling is used to exploit the instruction level parallelism(ILP)inherent in program through reordering its instructions.

Improving the degree of the instruction level parallelism is not only an important trend for the development of the CPU architecture but also significant content of the course about "Computer Organization", "Computer Architecture".

ILP Based Multimedia Realtime Processing;

In order to exploit instruction level parallelism(ILP),multiple functional units with multi-ports register file are often used in very long instruction word(VLIW) processor.

This paper presents the architecture and implementation approach of multimedia data processing on the ILP(Instruction Level Parallelism)of DSP platform.