1) local address decoder
局部地址译码器;局部地址译码器
2) address decoder
地址译码器
1.
Design of a Novel Structure of Sense Amplifier and Address Decoder Applied in a SRAM;
SRAM中新型结构的灵敏放大器及地址译码器的设计
2.
According to the study of the design of address decoder in microcomputer application system, a simple method of designing an arbitrary address range decoder with programmable logic device (PLD) is put forward.
通过对微机应用系统中地址译码器设计方法的探讨 ,指出了传统 MSI器件的局限性 。
3.
At first,this paper analyces the open defect of CMOS RAM address decoder,it comes out that one type open defect cannot be detected by march test algorithm,and then we give the test method of this type undetectable fault and the design scheme with built in tolerance against hard to detect open defects.
对 CMOS存储器中地址译码器的开路故障进行了分析和分类 ,得出了其中有一类开路故障不能用常用的测试算法可靠的测试出 ,给出了测试该类开路故障的测试方法以及针对该类开路故障的容错性设计方
3) Network address translator(NAT)
网络地址译码器
4) interface address decoder
接口地址译码器
5) starting address decoder
起始地址译码器
6) Address decoding
地址译码
1.
For the Flexibility, the FPGA could achieve address decoding and the calculation of signal amplitude and then control the signal attenuation base on the amplitude.
通信控制系统是整机系统中必不可少的一部分,该系统的设计主要是以DSP和FPGA作为硬件资源,利用DSP的高速性实时的实现与上位机和各个分机之间的数据通信,利用FPGA的灵活性实现地址译码和信号幅度的计算,并且可以根据信号幅度控制信号的衰减,16c550芯片和HPI为该系统提供了外部通信接口。
补充资料：局部
一部分；非全体：～麻醉 ㄧ～地区有小阵雨。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条