1) full decode address
全译码地址
2) Address decoding
地址译码
1.
For the Flexibility, the FPGA could achieve address decoding and the calculation of signal amplitude and then control the signal attenuation base on the amplitude.
通信控制系统是整机系统中必不可少的一部分,该系统的设计主要是以DSP和FPGA作为硬件资源,利用DSP的高速性实时的实现与上位机和各个分机之间的数据通信,利用FPGA的灵活性实现地址译码和信号幅度的计算,并且可以根据信号幅度控制信号的衰减,16c550芯片和HPI为该系统提供了外部通信接口。
3) address coding
地址译码
1.
On the basis of analyse in depth the function characteristics and corresponding signal actions of external bus port of ADSP2106X, this paper discussed the problems such as address distribute and address coding needed to be considered as expanding external memories and interfaces for ADSP2106X,and presents the concrete design examples.
在深入分析ADSP2106X外部总线口功能特点和相应信号作用的基础上,详细讨论了在给ADSP2106X扩展片外存储器和接口时应考虑的地址分配和地址译码方法等问题,并给出了具体设计方法实例。
5) address decoder
地址译码器
1.
Design of a Novel Structure of Sense Amplifier and Address Decoder Applied in a SRAM;
SRAM中新型结构的灵敏放大器及地址译码器的设计
2.
According to the study of the design of address decoder in microcomputer application system, a simple method of designing an arbitrary address range decoder with programmable logic device (PLD) is put forward.
通过对微机应用系统中地址译码器设计方法的探讨 ,指出了传统 MSI器件的局限性 。
3.
At first,this paper analyces the open defect of CMOS RAM address decoder,it comes out that one type open defect cannot be detected by march test algorithm,and then we give the test method of this type undetectable fault and the design scheme with built in tolerance against hard to detect open defects.
对 CMOS存储器中地址译码器的开路故障进行了分析和分类 ,得出了其中有一类开路故障不能用常用的测试算法可靠的测试出 ,给出了测试该类开路故障的测试方法以及针对该类开路故障的容错性设计方
6) address changeable decoding
可变地址译码
补充资料：全食谱购买地小全
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