1) loop phase locking
环路相位锁定
2) PLL(Phase lock loop)stability
锁相环路稳定性
3) phase-looked loop
相位同步回路，锁相环路
4) phase locked loop
锁相环路
1.
An example of the phase locked loop applied in the phase adjusting trigger was given in this paper.
锁相环路是完成两个电信号相位同步的反馈控制系统,适宜于变流装置的同步触发电路之中。
2.
The basic principle of using phase locked loop technique to realize the design and analysis of program controlled frequency syntheses was introduced.
本文简要地叙述了应用锁相环路实现信号合成的基本原理。
3.
Pulse width modulation and phase locked loop are adopted to reduce the complexity of clock recovery circuits.
采用PWM(脉宽调制)技术和PLL(锁相环路)结构,降低了CRC(时钟恢复电路)的复杂程度。
5) Phase-locked loop
锁相环路
1.
The standarded frequency is formed by the Single-chip computer setting an setting value to timing counter, and the phase-locked loop produces diffrents frequencies discreted for output.
叙述了由单片机、定时计数器 82 5 3-5及单片集成锁相环路组成的可程控频率合成技术 ,而标频可经单片机设定预置值给定时器T1 而形成 ,并经锁相环路产生各种离散的频率输出。
6) PLL
锁相环路
1.
Special PLL used in target RF simulation of the radio detonator;
引信目标射频仿真中的特殊锁相环路
2.
PLL Design in Digital Receiver for Nonbalanced BPSK Modulation and Realize on FPGA;
非平衡BPSK调制数字接收机锁相环路设计及其FPGA实现
3.
This paper introduces the application of PLL frequency synthesizer, its total plan of single-chip microcomputer control,design of the main circuits, programming, adjuste-ment, measurement results and improvement.
介绍了锁相环路频率合成器的应用、由单片机控制的大规模集成锁相环频率合成器总体方案、主要电路的设计与编程、调测结果及其改进。
补充资料：相性自性
【相性自性】
览而可别曰相。谓由前第一义心所集万善之因，各有自相形于外故，是名相性自性。
览而可别曰相。谓由前第一义心所集万善之因，各有自相形于外故，是名相性自性。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条