Compared with the synchronized counter,the asynchronous counter faced two prominent difficult questions in design: One is the selection of clock signals of various triggers,the other is the correct gain of the karnaugh map at the time when the is simplified into the equation of state for varions triggers.

On the base of the traditional approaches for designing synchronous sequential circuits,a new approach for designing asynchronous sequential logic circuit is proposed in this paper where the trigger pulses can be directly obtained from sequential waveforms in sequential circuits,and the next state Karnaugh maps can be acomplished according to the state transformations caused by clock signals.

This paper introduces IBIS model and its applications in the design of computer high-speed system, and gives the waveform of clock signal simulation in detail.

With the development in computer,semiconductor and communication technology,the signal clock in a circuit system works faster and the signal rise time gets shorter.

The extinction ratio of optical clock signal can be greatly increased after passing through birefringent fiber loop mirror(FLM, due to its flexibly tunable filtering characteristics,and then the clock signal quality is improved.

Base on the comparison of each kind of structure of toggle flip-flop(TFF),using a high-speed frequency divider circuit structure,which controlled by single clock signal to achieve,the design and realization of a 1∶8 frequency divider for optical fiber communication is introduced.