Four new subdivision principles based on computer clock pulse are presented, and their corresponding hardware block diagrams realizing real time measurement are also given out, which are mainly used for the processing of phase or frequency modulate typed sensor signal in gear transmission error measurement of machine tool.

It can be obtained more accurately by analyzing the time-impulse signal of a shaft,which is picked by using a phot.

Compared with the synchronized counter,the asynchronous counter faced two prominent difficult questions in design: One is the selection of clock signals of various triggers,the other is the correct gain of the karnaugh map at the time when the is simplified into the equation of state for varions triggers.

On the base of the traditional approaches for designing synchronous sequential circuits,a new approach for designing asynchronous sequential logic circuit is proposed in this paper where the trigger pulses can be directly obtained from sequential waveforms in sequential circuits,and the next state Karnaugh maps can be acomplished according to the state transformations caused by clock signals.

This paper introduces IBIS model and its applications in the design of computer high-speed system, and gives the waveform of clock signal simulation in detail.

With the development in computer,semiconductor and communication technology,the signal clock in a circuit system works faster and the signal rise time gets shorter.