This paper proposes a new methodology to design highly-balanced and highly-reliable front-end controllable clock tree,and solves the problem that clock tree has to be designed iteratively until performance and power dissipation requirements are met in back-end flow.

The equivalent checking in the formal verification was through the whole of digital circuit back-end design, such as: the comparison between RTL and netlist; the one between netlist and layout.

Taking the back end design of bluetooth baseband chip for example, the article introduces the semi custom ASIC design flow and design principles by using the auto place & route tool .