1) digital frequencylocked loop
数字锁频环
2) digital phase locked loop
数字锁相环
1.
Design of all digital phase locked loop based on VHDL;
基于VHDL的全数字锁相环的设计
2.
A new digital phase locked loop based on FPGA
一种新型数字锁相环的设计
3.
DSP TMS320LF2407A was adopted to realize digital phase locked loop,sample parameters during induction heating process and realize constant current control algorithm.
DSP采用TMS320LF2407A,主要用于实现数字锁相环、参数采样和恒流控制算法;CPLD采用EPM7128,主要用于完成驱动死区时间设置,并由此芯片来完成系统中其它逻辑控制功能。
3) Digital PLL
数字锁相环
1.
Design of Digital PLL Based on FPGA;
基于FPGA的数字锁相环的设计
2.
Design of a new digital PLL in ASIC algorithm;
数字锁相环的ASIC设计
3.
Realization of digital PLL frequency synthesizer with CPU controlling on FPGA;
CPU控制的数字锁相环频率合成系统的FPGA实现
4) digital phase-locked loop
数字锁相环
1.
Extending locked range of digital phase-locked loop by prediction estimation of states;
状态预估法扩展数字锁相环的锁相区间
2.
A speed-measured way based on digital phase-locked loop of FPGA;
一种基于FPGA的数字锁相环测速实现方法
3.
Design of Digital Phase-Locked Loop Based on FPGA
基于FPGA的数字锁相环设计
6) digital phase locked loops
数字锁定环
补充资料：锁环
1.锁链。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条