1.
Research and Design of All-digital PLL with High Frequency and Low Jitter Performance;
高速低抖动全数字锁相环的设计研究
2.
APPLICATION OF ISPLSI1016 IN DIGITAL PHASE-LOCKED LOOP;
ispLSI1016在数字锁相环中的应用
3.
Detetion of Harmonic Waves Based on DPLL Synchronous Sampling
基于数字锁相环同步采样的谐波检测
4.
Design of Digital Phase Locked Loop Used in SDH Equipment Clock
SDH设备时钟中的数字锁相环设计
5.
The Implementation and Analysis of Digital Phase-locked Loop Based on FPGA
基于FPGA的数字锁相环实现与性能分析
6.
Design of all digital phase locked loop based on FPGA
基于FPGA的全数字锁相环的设计
7.
Research on Adpll-Basedtime Digital Converter
基于全数字锁相环的时间数字转换器的研究
8.
Design of Frequency Scanner Based on Delta-Sigma Fractional-N PLL LMX2471
基于小数分频数字锁相环LMX2471的扫频仪设计
9.
Research on All Digital Phase-Locked Loop with High Precision Automatic Modulus Control;
高精度自动变模控制全数字锁相环的研究
10.
Design of Temperature Frequency Conversion Circuit Based on Digital Phase Locked Loop;
基于数字锁相环的温控变频电路的设计
11.
Realization of LL-DPL in FPGA/CPLD
超前滞后型数字锁相环LL-DPLL在FPGA/CPLD中的实现
12.
A New Low Power All-Digital PLL Design Based on VHDL
基于VHDL的一种低功耗新型全数字锁相环设计
13.
Automatic Modulus Controlled All Digital Phase Locked Loop with Large Lock-in Range
一种自动变模控制的宽频带全数字锁相环
14.
FPGA-based high-performance all-digital phase-locked loop design
基于FPGA的高性能全数字锁相环设计与实现
15.
Design of an Improved Architecture for Fast Locking DLL Used in FPGA
一种改进的用于FPGA的快速数字锁相环电路设计
16.
Design and Implementation of An Improved Digital Phase Locked Loop Based on VHDL
基于VHDL的一种改进型数字锁相环的设计与实现
17.
A New Type ADPLL Used in High-Frequency Induction Pyrogenation System
全数字锁相环高频感应加热系统的设计
18.
A Novel All-digital Phase-locked Loop Z-domain Model in Time Domain
一种新型的时间域全数字锁相环Z域模型