1) latch duration
闩锁时间
2) latch-up
闩锁
1.
Latch-up Free Design of SCR-Based ESD Protection Circuits
基于SCR的ESD保护电路防闩锁设计
2.
Based on the analysis of two protection methods,an over-current protection circuit which can improve the integrated regulators latch-up effect is proposed.
分析了两种过流保护方法的功能及优缺点,研究并提出了一种可应用于集成稳压器中改善闩锁效应的foldback过流保护电路。
3.
Several problems about latch-up experience in the reliability design of multiplex power supply systems are studied.
对在多级电源系统可靠性设计中遇到的几个关于闩锁的问题进行了研究,针对闩锁产生的原因进行分析,并提出解决方法。
3) latch up
闩锁
1.
Based on the analyzing of latch up issues in Power IC, a way was used to improvelatch up immunity, that is a minority carrier guarding which connects to GND between high voltagedevice and low voltage device.
在分析功率集成电路中闩锁效应的基础上,采取一种抗闩锁方法,即在高低压之间做一道接地的少子保护环。
2.
Controlled hole injection LIGBT (CI LIGBT) is proposed in the paper,which can effectively control the hole injection with high anode voltage,and its latch up free characteristics can be improved.
本文提出空穴注入控制型横向绝缘栅双极晶体管 (CI LIGBT) ,可有效控制高压下阳极区空穴注入 ,提高器件的抗闩锁性能 。
4) Latch
[英][lætʃ] [美][lætʃ]
闩锁
1.
The Latch Fault Caused by Radiation in Satellite Device and One Preventive Method;
空间通信设备的辐射闩锁故障及对策
2.
CMOS Circuit Latch Resulted from Leakage of Instrument;
仪器漏电引起的CMOS电路闩锁
3.
The supply voltage and output voltage(output voltage just before latch) of CMOS latch effect under different static gate trigger voltage(input voltage)are measured.
测试了不同静态栅极触发电压(输入电压)下诱发CMOS闩锁效应需要的电源电压和输出电压(即将闩锁时的输出电压),发现静态栅极触发CMOS闩锁效应存在触发电流限制和维持电压限制两种闩锁触发限制模式,并且此栅极触发电压-输出电压曲线是动态栅极触发CMOS闩锁效应敏感区域与非敏感区域的分界线。
6) Time-Lock
时间锁
1.
Implementation of the PLC Time-Lock;
一种PLC时间锁的实现方法
补充资料：锁模时间
分子式：
CAS号：
性质：又称锁模时间。对橡胶模压制品来说，指从模具完全闭合到完成硫化，卸开平板硫化机压力所用的时间。实际就是完成一次产品硫化所用的时间。
CAS号：
性质：又称锁模时间。对橡胶模压制品来说，指从模具完全闭合到完成硫化，卸开平板硫化机压力所用的时间。实际就是完成一次产品硫化所用的时间。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条