1) Carry antecedence method
超前进位法
2) Carry look-ahead adder
超前进位加法器
1.
Design of 16-bit carry look-ahead adder;
16位超前进位加法器的设计
2.
In a computer,which is comprised of some logic parts with serial logic functions,the adder is the most basic and important logic circuit,but the traditional rapid adder circuit uses the carry look-ahead adder,which has some shortcomings,such as abnormity,needing long-line drive.
传统的快速加法器是使用超前进位加法器,但其存在着电路不规整,需要长线驱动等缺点。
3) carry look ahead adder
超前进位加法器
1.
In this paper,the principle of DDS is introduced firstly,and the module of mirrored adder and carry look ahead adder are set up,with the compared,it shows that mirrored adder is better than carry look ahead adder in arithmetic speed and layout.
分别利用镜像电路和超前进位全加器实现信号源累加器模块,进行模拟仿真并比较,结果表明镜像加法器在运算速度、版图布局上都优于超前进位加法器。
4) CLA
超前进位加法器
1.
With the advantages of CPA,CSA,CLA and PPA,a hybrid adder is proposed,which introduces a modified parallel prefix cell of Knowles s tree.
采用改进的 Knawles 树前缀运算单元,结合行波进位加法器、进位选择加法器、超前进位加法器和并行前缀加法器的优点,提出了一种混合结构的加法器。
5) carry lookahead adder
超前进位加法器
1.
The delay time formulae of the carry lookahead adders(CLA) were given based on the standard delayed model of logic gate and optimal circuit unit.
从门电路标准延迟模型出发 ,在超前进位加法器单元电路优化的基础上 ,给出了超前进位加法器延迟时间公式 ,阐明了公式中各项的意义 。
6) carry-lookahead
超前进位
1.
Variable-sized blocks,complementary carry logic between blocks and multilevel carry-lookahead logic within blocks are used to achieve a high-performance adder.
该文提出了一种以两位加法器模块构成的静态进位跳跃加法器,通过对加法器尺寸的优化方块分配、方块之间的互补进位产生以及方块内部的多级超前进位逻辑3种方法获得快速静态进位跳跃加法器。
2.
A fast carry-skip adder is proposed based on variable-sized two-level block carry-lookahead logic.
提出了一种基于方块超前进位的快速进位跳跃加法器。
补充资料：二进位制
数的一种表示法。只使用0 和1 两个记号，逢二进一。便于用物理状态表示。电子计算机的结构中主要采用二进位制.
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条