1) 4-bit carry look-ahead adder
4位超前进位加法器
2) Carry look-ahead adder
超前进位加法器
1.
Design of 16-bit carry look-ahead adder;
16位超前进位加法器的设计
2.
In a computer,which is comprised of some logic parts with serial logic functions,the adder is the most basic and important logic circuit,but the traditional rapid adder circuit uses the carry look-ahead adder,which has some shortcomings,such as abnormity,needing long-line drive.
传统的快速加法器是使用超前进位加法器,但其存在着电路不规整,需要长线驱动等缺点。
3) carry look ahead adder
超前进位加法器
1.
In this paper,the principle of DDS is introduced firstly,and the module of mirrored adder and carry look ahead adder are set up,with the compared,it shows that mirrored adder is better than carry look ahead adder in arithmetic speed and layout.
分别利用镜像电路和超前进位全加器实现信号源累加器模块,进行模拟仿真并比较,结果表明镜像加法器在运算速度、版图布局上都优于超前进位加法器。
4) CLA
超前进位加法器
1.
With the advantages of CPA,CSA,CLA and PPA,a hybrid adder is proposed,which introduces a modified parallel prefix cell of Knowles s tree.
采用改进的 Knawles 树前缀运算单元,结合行波进位加法器、进位选择加法器、超前进位加法器和并行前缀加法器的优点,提出了一种混合结构的加法器。
5) carry lookahead adder
超前进位加法器
1.
The delay time formulae of the carry lookahead adders(CLA) were given based on the standard delayed model of logic gate and optimal circuit unit.
从门电路标准延迟模型出发 ,在超前进位加法器单元电路优化的基础上 ,给出了超前进位加法器延迟时间公式 ,阐明了公式中各项的意义 。
6) 16-bit carry look-ahead adder
16位超前进位加法器
1.
Design of 16-bit carry look-ahead adder;
16位超前进位加法器的设计
补充资料：进位
加法中每位数等于基数时向前一位数进一，例如在十进位的算法中，个位满十，在十位中加一，百位满十，在千位中加一。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条