In this paper ,the unusual phenomena of TTL JK edge-triggered flip-flops are brought forth by experiment when the Cp edge s time is excessive long , and the cause of it is proved up , the formulae for the maxima of CP edge s time are set up as well , which is consistent with the practical measurement.

A Brief Analysis of the Drawing Techniques of JK Trigger s Oscillogram;

Taking the latch composed of two inverters as basic storage unit, this paper proposes a novel CMOS JK flip-flop based on the design at switch level.

A novel quantum logic element called MOBILE (monostable-bistable transition logic element) and its functional theory are introduced,and a synchronous set-reset edge-trigged JK flip-flop based on MOBILE is designed.

Taking JK flip-flop as an example, a minimization technique of J and K excitation functions based on behaviors of flip-flop was proposed.

Talking about one and only change of master-slave JK-FF;

Design of low power multivalued double-edge-triggered flip-flop;

The application of this type of double-edge-triggered flip-flop in seq.