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1)  wait for determine state difference table
待测状态差表
2)  wait for determine self state difference table
待测自状态差表
3)  graph state difference
表状态差
1.
Found operation laws of place state difference,order state difference,graph state difference,constituted incomplete state difference graph and self state difference graph,gave series important explains of incomplete state difference graph,according to several definitions of incomplete closed ascending order n ends output sequential machine.
根据不完全封闭n端输出顺序时序机的各种定义,建立了位状态差、序状态差、表状态差运算规律,构成了不完全状态差表及自状态差表,给出了不完全状态差表的一系列重要说明。
2.
According to several definitions of complete closed ascending order n ends output sequential machine,operation laws of place state difference,order state difference,graph state difference,constituted complete state difference graph and self state difference graph are founded,and series important properties of complete state difference graph are derived.
根据完全封闭升序n端输出时序机的各种定义,建立了位状态差、序状态差、表状态差运算规律,构成了完全状态差表及自状态差表,导出了完全状态差表的一系列重要性质。
4)  self state difference graph
自状态差表
1.
Found operation laws of place state difference,order state difference,graph state difference,constituted incomplete state difference graph and self state difference graph,gave series important explains of incomplete state difference graph,according to several definitions of incomplete closed ascending order n ends output sequential machine.
根据不完全封闭n端输出顺序时序机的各种定义,建立了位状态差、序状态差、表状态差运算规律,构成了不完全状态差表及自状态差表,给出了不完全状态差表的一系列重要说明。
2.
According to several definitions of complete closed ascending order n ends output sequential machine,operation laws of place state difference,order state difference,graph state difference,constituted complete state difference graph and self state difference graph are founded,and series important properties of complete state difference graph are derived.
根据完全封闭升序n端输出时序机的各种定义,建立了位状态差、序状态差、表状态差运算规律,构成了完全状态差表及自状态差表,导出了完全状态差表的一系列重要性质。
5)  waitng moving condition
待发状态
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6)  waiting states
等待状态
1.
Taking TMS320F206 as an example,the paper probes into the hardware design anddebug of the DSP system, assembly line conflict of software design, the setting of waiting states andhow to utilize the flash memory and so on.
以TMS320F206为例,着重探讨了DSP系统开发过程中的硬件设计与调试、软件设计中的流水线冲突、等待状态设置以及如何利用闪速存储器等相关问题。
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补充资料：待差
1.谓官吏等候调任新职。
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