1) spread spectrum clock generator(SSCG)
展频时钟
2) Spread-Spectrum-Clock Generation(SSCG)
扩展频谱时钟
1.
The Spread-Spectrum-Clock Generation(SSCG) technique is the latest technology to decrease electromagnetic radiation of the electronic system.
扩展频谱时钟技术是一种用来降低电子系统电磁辐射的最新技术,近年来在国外已被成功地用于以微处理器为核心的电子设备以及外设。
3) clock base frequency
时钟基频
1.
A new tool that can test the clock base frequency error of energy measuring devices and provide GPS standard time to calibrate real-time clock was introduced in this paper.
介绍了一种用来测量电能计量装置的时钟基频误差,并提供GPS标准时间以校准其实时时钟的新型工具。
4) clock frequency
时钟频率
1.
This paper introduces A/D Converter ICL7135 Series Collection in Single-chip Microcomputer Voltage Meter,interface circuit and clock frequency of AT89C51 and ICL7135.
介绍了双积分A/D转换器ICL7135与AT89C51进行串行数据采集的原理、接口电路的连接方法及时钟频率选择,并且通过实验数据及图形证明了该方法的可行性。
2.
The relations among the error of frequency measurement, measure time, reference clock frequency and the measured signal frequency, are also deduced.
本文针对计数式瞬时测频精度进行分析,提出了通过级数展开来估计测频误差的方法,其中应用了莱布尼兹定理对交错级数进行了取舍,推导出计数式瞬时测频中测频误差与观测时间、基准时钟频率及被测信号频率之间的关系。
3.
Dynamic voltage scaling (DVS) technique is an effective way to reduce processor energy consumption through changing the processor’s supply voltage and clock frequency at the runtime.
动态电压缩放技术是一种能有效优化处理器能耗的方法,它允许处理器在运行时动态地改变其时钟频率和供电电压。
5) clock division
时钟分频
1.
Frequency-tunable all-optical clock division using semiconductor laser subjected to external optical injection;
外光注入半导体激光器实现重复速率可调全光时钟分频
2.
This paper studied clock division phenomenon on SOA injection Mode-Locked Fiber Laser,and the focus of the injection repetition frequency of 5.
对半导体光放大器(semiconductor optical amplifier:SOA)注入锁模光纤环激光器的时钟分频现象进行了实验研究,重点分析了注入重复频率为5。
3.
The high-repetition rate optical pulses clock division is investigated based on the nonlinear dynamics of optically injected Fabry-Pérot semiconductor laser.
16 GHz光脉冲输出的时钟分频现象,讨论了Fabry-Pérot半导体激光器的偏置电流、注入光功率、注入光光谱以及光谱线宽等因素对时钟分频的影响。
6) clock frequency error(CFE)
时钟频偏
1.
The model between a switch under tested(SUT) and a Smartbits card is presented and used for two interconnecting switches,this paper presents that clock frequency error(CFE) between a SUT and a Smartbits card is a leading factor of forwarding delay in an ethernet switch.
以测试交换机和Smartbits测试卡作为两个对接交换设备的模型,提出了时钟频偏是交换机转发时延的主要影响因素。
补充资料:齐展展
1.整整齐齐。
说明:补充资料仅用于学习参考,请勿用于其它任何用途。
参考词条