1) Duty cycle corrector
占空比调整电路
2) duty-cycle corrector
占空比调节电路
1.
A simple full-digital 50% duty-cycle corrector(FD-DCC)with the principle of digital delay lines and pulse generators,is presented in this paper with high performance to produce non-skew and high-quality clocks.
利用数控延迟线原理和脉冲电路特性设计实现了一种纯数字方式的高性能时钟50%占空比调节电路FD-DCC(Full-Digital Duty-Cycle Corrector),不包括任何反馈环路,可产生无偏时钟。
3) adjustable duty ratio
占空比可调
1.
This paper presents that developing ultrahigh frequency pulse EDM generator of adjustable duty ratio by CPLD based on the characteristic of CPLD,complete hardware logistic.
从CPLD具有完全硬件逻辑的特点出发,提出了用CPLD发生占空比可调的超高频电火花加工脉冲信号的设想。
2.
Also developing ultrahigh frequency pulse celectro-discharge machining(EDM) generator of adjustable duty ratio by CPLD based on the characteristic of CPLD,complete hardware logistic.
从CPLD完全硬件逻辑的特点出发,使用CPLD发生占空比可调的超高频EDM脉冲信号。
4) duty-cycle correction
占空比调节
1.
The novel features of the proposed DCC include a higher reliability against process,voltage and temperature(PVT) variation due to the use of the synchronous mirror delay(SMD) technique,no-skew output clock,and much faster duty-cycle correction speed compared to conventional DCC s.
本文介绍了采用纯数字相位合成法设计的高性能时钟50%占空比调节电路PB-DCC(Phase-Blending Du-ty-Cycle Corrector)。
5) PWM
占空比调制
6) Digital duty cycle measuring circuit
数字占空比检测电路
补充资料：占占
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