1) clock frequency error(CFE)
时钟频偏
1.
The model between a switch under tested(SUT) and a Smartbits card is presented and used for two interconnecting switches,this paper presents that clock frequency error(CFE) between a SUT and a Smartbits card is a leading factor of forwarding delay in an ethernet switch.
以测试交换机和Smartbits测试卡作为两个对接交换设备的模型,提出了时钟频偏是交换机转发时延的主要影响因素。
2) clock frequency deviation
时钟频率偏差
3) sampling clock frequency offset
采样时钟频率偏差
1.
Three different sampling clock frequency offset and residual frequency offset estimation methods were developed to improve their estimation accuracy in internet protocol-orthogonal frequency division multiple access(IP-OFDMA)system,and the characteristics of the pilot structure in IP-OFDMA system was considered.
为提高基于网络协议的正交频分多址(IP-OFDMA)系统中采样时钟频率偏差与残余频偏的估计精度,结合IP-OFDMA的自身导频结构特点,对经典估计方法进行改进,提出3种不同采样时钟频率偏差与残余频偏的估计方法。
4) clock skew
时钟偏差
1.
A yield driven clock skew scheduling algorithm is proposed in presence of process variations.
针对工艺参数变化的情况,提出一种成品率驱动的时钟偏差安排算法。
2.
This paper presents an effective approach for clock skew scheduling that can reduce the center error square and assign slacks incrementally.
提出了在时钟偏差规划过程中减小中心误差平方值的增量式松弛量分配方法。
3.
In multi-FPGA designs, the delay of clock transfer causes a huge clock skew between FPGAs and therefore undermines the system performance.
在多FPGA设计中,时钟信号的传输延时造成了FPGA间的大时钟偏差,进而制约系统性能。
5) clock skew
时钟偏移
1.
In this paper, the constitution of the synchronous digital system and the definition of clock skew are introduced, and a designing method for clock tree is presented.
文中介绍了同步数字系统的组成和时钟偏移的定义,提出了一种时钟树结构的设计方法,基于该方法用布局布线工具Astro对一个8051芯片进行了自动时钟树分析和指定结构的时钟树分析。
2.
The generation principle of clock skew was analyzed taking a SMIC 0.
目前的ASIC设计中,时钟偏移成为限制系统时钟频率的主要因素,时钟树综合技术通过在时钟网络中插入缓冲器来减小时钟偏移。
3.
Clock skew is in a synchronization digital integrated circuit design difficult problem.
时钟偏移是同步数字集成电路设计中的一个难题。
6) clock skew
时钟偏斜
1.
A new clock skew scheduling algorithm is proposed.
提出了一种新的时钟偏斜规划算法,该算法所生成的时序约束可以有效地促进逻辑综合工具的面积优化。
2.
Mechanism about the clock skew of synchronism sequential circuit has been presented, based on analyzing the characteristics of programmable resources and sequential circuit in FPGA.
在分析星载FPGA内时序电路特性以及FPGA可编程资源特性的基础上,指出了FPGA内同步时序电路出现时钟偏斜现象的机理。
3.
Nowaday, active deskew circuits are widely used for clock skew elimination.
在这种情况下，时钟偏斜已经成为制约频率提升的主要因素。
补充资料：导航时钟
| 导航时钟 navigation clock 飞行器上供领航计算用的计时仪器。它能指示地方时间或法定时间（如北京时间）以及飞行时间。在绕地球飞行的载人飞船上，时钟指示格林尼治时间、已飞行时间和法定时间。老的导航时钟都是机械式的，现代飞行器上已采用精度很高的电子时钟。导航时钟在原理上与地面用的时钟无异 ，但在结构上要能经受航空和航天的恶劣环境条件。导航时钟具有年、月、日、星期等显示功能，还有按规定时间报时的功能，以便于航天员安排休息。 |
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条