Like multi-core general processors,MC-DSPs with memory-shared structures often suffer from the long access latency involved in cache coherency operations.

After introducing bus transaction and cache attribute of memory area in multiprocessor system based on P6 bus, this paper discusses hardware snoopy mechanism of P6 bus, then discusses MESI state transitions adopted by Pentium Ⅲ processor, and finally focuses on how the multiprocessor and the P6 bus cooperate to ensure Cache coherency of the whole system.

Method for solving Cache coherence in SMP of shared virtual memory;

Research of cache coherence in website s cache design;

This paper overviews the coherence issue of Cache and the current research on this issue, and based on existing Cache coherence protocols, puts forward an improved Cache coherence protocol and the architecture of chip multiprocessors (CMPs) applied for this protocol.

Method of data consistency maintenance based on web service;

Data independence data consistency and corresponding solution involved between local data and ERP integration are discussed in this paper.

NET and solve the data exchange problem between outside window subsystem and inside local network subsystem,we designed the solution on the dynamical link between the system and many kinds of databases,and studied the method for keeping the data consistency on servers of network interconnection.

The excellent process ability of TTA pipeline gave high demands to the data cache.

On the basis of deep researches on the data Cache working mechanism and the static random access memories (SRAMs) te.

In order to reduce the leakage energy,the set-association data caches are divided into several memory banks.