1) 3-input floating-point adder
3输入浮点加法器
2) floating-point adder
浮点加法器
1.
An Approach of Design for High-Speed Floating-point Adder;
一种高速浮点加法器的设计实现
2.
Floating-point LMS Algorithm is implemented successfully based on the multi-input structure-efficient floating-point adder presented.
文中根据多输入高效浮点加法器结构在FPGA(现场可编程门阵列)上实现了浮点LMS算法。
3) Floating point adder
浮点加法器
1.
Floating point adder is an important block in IC datapaths Its performance and power consumptions have a great effect on the performance of processors and DSP s In this paper, several architectures for floating point adder are summarized and analyzed A low power triple datapath architecture is described in particular Finally, the practicability of floating point adder architecture has been analyze
浮点加法器是集成电路数据通道中重要的单元 ,它的性能和功耗极大地影响着处理器和数字信号处理器的性能。
4) floating input
浮点输入
5) three-input adder
全加法器，三输入加法器
6) two-input adder
双输入加法器，半加[法]器
补充资料：加法器
产生数的和的装置。加数和被加数为输入，和数与进位为输出的装置为半加器。若加数、被加数与低位的进位数为输入，而和数与进位为输出则为全加器。常用作计算机算术逻辑部件，执行逻辑操作、移位与指令调用。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条