1) sequential equivalence checking
时序电路等价验证
1.
A new frame-expansion based sequential equivalence checking algorithm is proposed.
提出一种改进的基于时间帧展开的时序电路等价验证算法,其来源于模型检查中的基于数学归纳的验证算法,在使用并简化了SAT问题中不可满足子集提取过程后,将基本条件检查和归纳检查合并处理。
2.
A sequential equivalence checking algorithm based on state transfer graph is presented.
提出一种基于状态转换图的时序电路等价验证算法。
2) Sequential equivalence verification
时序等价验证
3) verify sequential circuit
时序电路的验证
4) equivalence verification
等价验证
1.
According to the results of polynomial function,the upper bound of simulated vectors is obtained for the equivalence verification of the fixed-point datapaths,which avoids the exhaustive simulation.
为证明定点数据通路的定点算术规范与转换后的寄存器传输级实现是等价的,结合算术转换和多项式函数对实现序列加法、乘法、移位运算的定点数据通路进行建模,根据多项式函数的结论得到对定点数据通路进行等价验证所需要的模拟向量数的上界,避免穷举所有的模拟向量。
2.
Because of this,formal verification methods,such as equivalence verification,have become important for register transfer level or behavioral level verification.
基于BDD或布尔SAT的等价验证方法虽然能够成功验证低层次门级电路,但却难以满足高层次设计验证要求。
5) timing verification
时序验证
1.
An approach how to check the setup time and the hold time of the integrated circuit port signal with the aid of the timing check system in the integrated circuit timing verification stage is introduced in this article.
论文介绍了在集成电路时序验证阶段如何借助时序检测系统对集成电路端口信号的建立时间和保持时间进行检测。
2.
A timing verification research on the general processor used for communication and network is written in this dissertation.
论文对一个用于通信和网络的通用通信处理器的时序验证进行了研究。
6) equivalence checking
等价性验证
1.
Automatic operand ordering for equivalence checking;
等价性验证中的自动算符排序
2.
Latch mapping algorithm for equivalence checking;
面向等价性验证的锁存器匹配算法
3.
An Equivalence Checking Algorithm for Combinational Circuits;
带黑盒组合电路的等价性验证
补充资料：时序女神
时序女神(horae)：宙斯和忒弥斯诸女，
欧诺弥亚(eunomia）秩序女神
狄刻(dike)公正女神
厄瑞涅(eirene）和平女神.
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条