1) Timing Loop
定时环
2) timing lo
定时环路
1.
This paper discusses the SDH’s synchronization and timing and its influence on synchronous network,then gives two kinds of methods on how to avoid timing loop.
首先讨论了传输系统中引入 SDH网后对数字时钟同步网的影响及 SDH网本身的同步定时问题 ,并给出两种避免定时环路的方法。
4) tailing self-time
定时自环
1.
The tailing self-time is often portrayed as the archenemy of the network system.
定时自环是通信网络中的大敌,在定时自愈安排中,必须绝对避免定时自环隐患。
5) cycle timer
循环定时器
1.
This paper presents a kind of cycle timer, which times accurately and by which two state times can be regulated freely and the two states can be changed any time.
该循环定时器具有计时准确，任意选择两个状态的时间，工作状态和计时起点随时改变的特点，可用于工业和家用电器的控制
6) DLL
延时锁定环
1.
This paper presents a delay-locked loop(DLL)-based 1.
设计并实现了一个基于延时锁定环(DLL)、用于超宽带(UWB)无线通信系统的1。
2.
This paper presents a delay locked loop (DLL) circuit that can be implemented with fully digital circuits.
介绍了一种区别于锁相环 (PLL )和基于压控延迟线 (VCDL )的延时锁定环 (DLL )、全部由纯数字电路实现的 DL L电路。
3.
FPGA provides four fully digital dedicated on-chip Delay-Locked Loop(DLL) circuits, Which provides zero propagation delay, low clock skew between output clock signals distributed throughout the device, and advanced clock domain control.
FPGA(现场可编程逻辑门阵列 )内部集成了四个全数字片内延时锁定环电路 (Delay -LockedLoop ,缩写为DLL) ,利用它能够实现对芯片输入时钟的零延时输出和时钟倍频 ,分频以及镜像操作等多种控制功能。
补充资料：报定时不定
【报定时不定】
谓业力定故，报不可改，然时有可转，故时节不定，是名报定时不定。
谓业力定故，报不可改，然时有可转，故时节不定，是名报定时不定。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条