1) deep submicron
深亚微米
1.
Analyzing short channel effects in deep submicron MOSFET s using variational method;
深亚微米MOSFET短沟效应的变分法分析
2.
The deep submicron technology presents lots of new challenges to the physical design of VLSI and new techniques are needed in the back-end design flow.
深亚微米下芯片的物理设计面临很多挑战,特别是对于超大规模电路,在后端设计流程上要有新的方法。
3.
With development of the VLSI circuits towards the deep submicron and the ever-increasing density of integrated circuits,interconnection delay becomes a limiting factor for increasing device speed.
随着VLSI向深亚微米发展、集成电路密度不断提高,互连延迟成了加快器件速度的一个限制因素,由于互连延迟是由金属连线间的电阻及电容所产生的,因此萃取寄生参数的工作更显重要。
2) deep sub-micron
深亚微米
1.
A novel bus coding scheme for low power in deep sub-micron technologies;
一种深亚微米工艺下的总线低功耗编码方案
2.
With the advent of the era of deep sub-micron IC, the feature size on the IC chip is shrunk to nanometers.
伴随着深亚微米集成电路时代的来临,芯片的特征尺寸已经缩小到纳米尺度。
3) deep-submicron
深亚微米
1.
PAE (Process Antenna Effect) is a key point in deep-submicron VLSI design due to its negative influence.
深亚微米超大规模集成电路(VLSI)中金属互连线的天线效应(PAE)将会严重影响芯片物理设计的结果,甚至造成设计的失败。
2.
18 μm CMOS low power Sigma-Delta ADC modulator,a new deep-submicron mixed-signal system design method is presented in this paper.
18μm CMOS工艺、低功耗Sigma-Delta ADC调制器(SDM)部分的设计研究,提出了一种深亚微米下混合信号处理系统的设计方法,论述了从系统级行为验证到电路级验证的设计流程,与传统流程相比,在行为级验证中采用了SIMULINK建模方法,在电路级的验证中,提出了从宏模型验证到晶体管级细电路验证这样一种新颖的设计方案,其中所提出的宏模型以6。
3.
This paper presents the causes of crosstalk in deep-submicron integrated circuit design and its impact on signal integrity, and discusses the analysis and solution of this problem.
本文介绍了深亚微米集成电路设计中串扰的成因及其对信号完整性的影响,论述了串扰分析和设计解决的一般方法,对于实际设计具有一定的理论指导意义和应用参考价值。
4) DSM
深亚微米
1.
Static-Noise Margin Analysis on DSM SRAM Cell;
深亚微米SRAM存储单元静态噪声容限研究
2.
As the scale of integrated circuit enlarges and the speed increases, the back-end design in Deep Submicron (DSM) Technology has experienced a rapid development.
本文通过对传统大规模集成电路设计流程的优化,得到了更适合于深亚微米工艺集成电路的后端设计流程,详细介绍了包括初步综合、自定义负载线的生成、版图规划、时钟树综合、静态时序分析等,并通过前端和后端设计的相互协作对大规模集成电路进行反复优化以实现设计更优。
3.
In this paper the existing technology status of SoC and FPGA is presented in DSM.
文章论述当前深亚微米工艺条件下SoC、FPGA技术发展现状。
5) deep sub micron
深亚微米
1.
Based on the hydrodynamic energy transport model, the short channel effect immunity in the deep sub micron grooved gate PMOSFET is studied together with the influences of substrate and channel doping density on that effect immunity.
基于流体动力学能量输运模型 ,首先研究了槽栅器件对短沟道效应的抑制作用 ,接着研究了不同衬底和沟道杂质浓度的深亚微米槽栅PMOSFET对短沟道效应抑制的影响 ,同时与相应平面器件的特性进行了对比 。
2.
Based on the hydro dynamics energy transport model,the influence of channel and substrate doping densities on hot carrier effect immunity in deep sub micron grooved gate PMOSFET is studied and explained in terms of device interior physics mechanism.
基于流体动力学能量输运模型 ,利用二维仿真软件 Medici研究了深亚微米槽栅 PMOS器件衬底和沟道掺杂浓度对器件抗热载流子特性的影响 ,并从器件内部物理机理上对研究结果进行了解释。
3.
Based on the hydro dynamic energy transport model,the influences of structure parameters on the hot carrier effect immunity and the suppression of short channel effect in deep sub micron grooved gate PMOSFET are studied and explained in terms of the device interior physics mechanism.
基于流体动力学能量输运模型 ,利用二维仿真软件 Medici对深亚微米槽栅 PMOS器件的结构参数 ,如凹槽拐角、负结深、沟道和衬底掺杂浓度对器件抗热载流子特性和短沟道效应抑制作用的影响进行了研究 。
6) Sub-micron
深亚微米
1.
The SEE characteristic and hardening techniques of CMOS SRAM with sub-micron feature size are studied.
在空间环境甚至在地面环境中,受高能粒子等多种因素的的影响,深亚微米COMS SRAM很容易发生单粒子事件(single event effects,SEE),使得COMS SRAM中的存储数据发生翻转甚至直接将器件烧毁。
补充资料：热深厥深
热深厥深 热深厥深 病证名。指热厥证的征象。指邪热越深入，四肢厥冷的症状越严重，皆因阳气被遏，邪气内闭所致。属真热假寒证。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条