1) low leakage power
低静态功耗
1.
Compared with the current cache architecture for low power, this architecture with resizable ways and low leakage power has the characteristic of fewer additional logics, simpler .
该结构通过门控Gnd技术来动态地关闭或开启部分cache路,使得cache结构可以在低功耗配置和正常配置之间切换,从而达到降低静态功耗的目的。
2) low static power design
低静态功耗设计
3) standby power
静态功耗
1.
The paper analyses the standby power dissipation of standard SRAM 6-T cells.
为了解决存储单元的亚阈值泄漏电流问题,分析了在深亚微米下静态随机存储器(SRAM)6-T存储单元静态功耗产生的原因,提出了一种可以有效减小SRAM静态功耗浮动电源线的结构,并分析在此结构下最小与最优的单元数据保持电压;最后设计出SRAM的一款适用于此结构的高速低功耗灵敏放大器电路。
2.
As technology evolves, the threshold voltage will be re- duced accordingly, which results in an exponential increase of standby power.
随着工艺的发展,器件阈值电压的降低,导致静态功耗呈指数形式增长。
4) static power
静态功耗
1.
The static power exceed the dynamic power in microprocessors as the feature size shrinks,especially for on-chip L2 caches.
随着集成电路制造工艺进入超深亚微米阶段,静态功耗在微处理器总功耗中所占的比例越来越大,尤其是片上二级Cache。
2.
Simulation results prove that active power of proposed Zipper CMOS full-adder can be reduced by up to 37%,5% and 7%,and static power can be reduced by up to 41%,20% and 43% as compared to the standard,the dual threshold voltage,and the multiple supply Zipper CMOS domino full-adder under similar delay time,respectively.
仿真结果表明,在相同的时间延迟下,与标准Zipper CMOS多米诺全加器、双阈值Zipper CMOS多米诺全加器、多电源电压Zipper CMOS多米诺全加器相比,新型Zipper CMOS多米诺全加器动态功耗分别减小了37%、35%和7%,静态功耗分别减小了41%,20%和43%。
5) Super-low quiescent powerdissipation current
超低静态功耗电流
6) static power management
静态功耗管理
1.
The PowerPC 603e microprocessor is a high performance, low cost, low power 32 b superscalar RISC microprocessor The architecture of PowerPC 603e is described briefly in this paper The technology of dynamic power management, static power management and some other low power design for PowerPC 603e are introduced in detail Finally the development status of PowerPC is presente
本文简要介绍了 Power PC6 0 3e结构 ,详细介绍了 Power PC6 0 3e动态功耗管理、静态功耗管理设计技术及一些低功耗技术 ,最后给出了 Power PC的发展现
补充资料：低都儿低
1.低而又低，很低。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条