1) Clock and data recovery
时钟数据恢复
1.
The receiver employs two 1:20 deserializers,an input signal pre-amplifier and clock and data recovery circuit.
接收器还包含了时钟数据恢复电路,其中的相位插值器通过改进编码方式,使得输出信号的幅度能够保持恒定,并且相位具有良好的线性度。
2.
This paper describes a clock and data recovery(CDR)circuit for RFID tag, and a new phase frequency detector(PFD) is proposed for this CDR circuit for NRZ data.
提出了一种适用于射频电子标签的时钟数据恢复电路,在电路中提出了一种适用于NRZ数据的新型鉴频鉴相器电路和自适应控制单元,能动态调节边沿检测器中延迟单元的延迟时间,使此时钟数据恢复电路具有大的锁定范围,且有结构简单易实现的特点。
3.
In serial data communication domain,clock and data recovery(CDR) using oversampling is a low-cost "fast retiming" technique that can be implemented as monolithic circuits using the standard digital CMOS process.
文中经过理论分析给出了一个基于过采样技术的时钟数据恢复电路(CDR)设计。
2) CDR
时钟数据恢复
1.
A high-speed and low-jitter CDR circuit for fiber-optic communications;
光纤通信用低相位抖动时钟数据恢复电路
2.
After comparing several CDR(Clock and Data Recovery) circuits,a new clock and data circuit based on the modified gated oscillator is proposed.
在吉比特级EPON的突发式接收模块中,时钟数据恢复是关键技术之一。
3.
Compared to the PLL, the input of CDR (Clock and Data Recovery) is high-speed random data, and the overall circuit works in a high speed input and high speed output status, all of this make the design of CDR difficult.
与锁相环相比,时钟数据恢复电路(Clock Data Recovery,CDR)的输入为高速随机数据,并且全部电路都工作于高速状态,使得时钟数据恢复电路的设计变得非常复杂;同时,时钟数据恢复电路也是PCI Express中最关键的部分,其带宽直接决定了整个系统的性能。
4) Clock and Data Recovery(CDR)
时钟和数据恢复
5) dual-loop clock and data recovery
双环时钟数据恢复
1.
The principle with the quadrature reference clocks in dual-loop clock and data recovery circuit was described.
描述了双环时钟数据恢复电路利用相位正交的参考时钟进行工作的原理,分析了传统的正交时钟产生方案,提出一种新的相位插值-选择方案并给出了CMOS电路实现。
6) parallel clock and data recovery
并行时钟数据恢复
1.
5Gbps/ch 2-channel parallel clock and data recovery circuit is designed and fabricated in TSMC s standard 0.
5Gbps/ch并行时钟数据恢复电路。
补充资料：数据通信网(见数据通信)
数据通信网(见数据通信)
data communication network
shu)u tongxinwang数据通信网(datac。mmunicati。nne饰ork)见数据通信。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条