New method testing the double fault of combinational circuits based on Boolean partial derivative.;

An algebraic method for detecting single fault of combinational circuits based on D algorithm;

Test set compaction for combinational circuit based on compact genetic algorithm;

Evolutionary Design of Combinational Circuits Based on Improved Genetic Programming;

A genetic algorithm was used for test generation, and the experimental results on some combinational circuits demonstrate the f.

The fault coverages achieved by the test generation procedures based on genetic algorithms are smaller than the deterministic test generation procedures for combinational circuits.

With the growth of the scale of integrated circuits,the design for test for combinatorial circuit in the chip and particularly in the SOC is becoming more and more important.

A leakage power reduction platform for CMOS combinational circuits by means of input vector control is presented.

A VSF-based leakage power evaluation model is then developed and used for evaluating and reducing the leakage power of CMOS combinational circuits.

Research on power analysis of CMOS combinational logic circuits;

The realization of a combinational logic circuit simulation platform with Applet technology of Java 2 is introduced in this paper.

The competitive risks simulation in combinational logic circuit can locate all the competitive risks in the example with rapidity and precision,and eliminate them effectively by the introduction of blockade pulse.