1) ULSI
甚大规模集成电路
1.
Investigation on the Final Polishing of Silicon Substrate in ULSI;
甚大规模集成电路制备中硅衬底精密抛光的研究
2.
The copper chemical-mechanical polishing (CMP) which is the key planarization technology for ULSI manufacturing was discussed.
对用于甚大规模集成电路(ULSI)制造的关键平坦化工艺———铜化学机械抛光(CMP)技术进行了讨论。
2) ultra large scale integration (ULSI)
甚超大规模集成电路
3) large scale integrated circuit
大规模集成电路
1.
This paper introduced and desinged an interface circuit by means of large scale integrated circuit PMM8713.
介绍了用大规模集成电路PMM871 3设计的控制和驱动 3相、4相步进电机的通用步进电机接口电路 。
2.
A compilation/generation method for test program of large scale integrated circuit (LSI), called Fault Simulation Method is presented in this paper.
本文叙述了一种名为故障模拟法的大规模集成电路的测试程序的编制、生成方法，这种方法主要是解决了随着大规模集成电路的发展，单个电路本身的输入／输出管脚数量不断增加，带来测试矢量呈现指数增长，从测试时间和测试成本上考虑，使用传统的穷举法已经不可能编制、生成出符合要求的大规模集成电路测试程序的问题。
4) LSI
大规模集成电路
1.
Research on Parallel Seam Sealing Process for LSI;
大规模集成电路的平行缝焊工艺研究
2.
A kind of super purification control system which can realize the high spotless environment for LSI s manufacturing is introduced.
介绍了一种实现大规模集成电路 (LSI)无尘生产环境的超净化控制系统 ,该系统的现场控制回路采用了先进的仿人工智能PID控制算法 ,这种算法避免了系统反馈滞后的振荡缺陷 ,利用LonWorks的网络技术 ,实现整体净化系统的智能化、可视化控制。
3.
The method will make the circuit more terse and reliable by using the LSI is pLSI1016 chip of lattice corporation as the core.
介绍了一种基于FPGA芯片设计FSK调制解调器的基本原理,并给出相应的VHDL语言描述,该设计以Lattice公司的大规模集成电路ispLSI1016芯片为核心,使得电路简洁、可靠性高。
5) VLSI
大规模集成电路
1.
Our algorithm not only avoids polynomial deflation but also is more efficient than traditional rootfinding algorithm and it is fit for being realized by VLSI.
该算法避免了多项式降次,计算量又远远小于经典的搜索算法,适于用大规模集成电路实现,而且可以推广应用于求解更高阶LSF参数。
2.
With the appearance of VLSI ATE,Auto test technology has been wide used,So production of IC validation is efficiency,This paper has introduced the typical flow of test in IC electric parameter,Then explain the basic principle of test and imaginable result.
随着大规模集成电路自动测试设备的出现,自动测试技术被广泛应用,实现了高效率的集成电路产品验证,这就使得应用自动测试设备有了一定的流程。
3.
With the development of VLSI(Very Large Scale Integration), the integrity becomes larger and larger, from hundreds of thousand to millions or tens of millions, and it becomes more difficult to finish the verification task.
随着大规模集成电路的发展,其设计规模不断增加,从几十万门级发展到百万、千万门级,完成相应的验证工作也变得越来越困难,给相应的验证工作带来了巨大的挑战。
补充资料：MOS集成电路
见金属-氧化物-半导体集成电路。
说明：补充资料仅用于学习参考，请勿用于其它任何用途。
参考词条