1.
A Code-matched Interleaver Design Based On The Low-bound of RSC Parity Weight
一种基于递归系统卷积码校验重量下限的匹配交织器设计方法
2.
VHDL Realization of Encoder and Decoder for Convolutional Code in Communication System
通信系统中卷积码编解码器的VHDL实现
3.
Research and Implementation of Convolutional Coding Algorithm in TD-SCDMA
TD-SCDMA系统卷积编码算法研究与实现
4.
Implement of a CRC and Convolution Encoding System Based on VHDL
基于VHDL语言的CRC加卷积编码系统
5.
Low-rate Convolutional Codes Used in Code-Spread CDMA System;
低码率卷积码在扩频通信系统中的应用
6.
Applied research of convolutional code and turbo code in VLF communication system
卷积码和Turb0码在甚低频通信系统中的应用研究
7.
The Performace Research of Convolution Code and Its Application in MIMO System;
卷积码的性能研究及其在MIMO系统中的应用
8.
Performance of convolutionally coded differential frequency hopping systems in partial-band jamming
卷积码差分跳频系统抗部分频带干扰的性能
9.
Research on an-based decode of Tail-biting convolutional codes and their performance analyses used to LTE system
LTE系统中截尾卷积码译码算法研究及仿真性能分析
10.
Convolution Code of the Viterbi Decoding FPGA to Achieve
卷积码Viterbi译码的FPGA实现
11.
compass integrated system compiler
积分罗经系统编码器
12.
Concatenated Reed-Solomon Product Code/Convolutional Code with Iterative Decoding
迭代译码的级联Reed-Solomon乘积码与卷积码
13.
Research on Decoding Tech of Convolutional Turbo Codes;
循环卷积Turbo码译码技术研究
14.
The Research of the Logic Algebra Decoding Method of (2, 1, 4) Convolutional Code;
（2，1，4）卷积码的逻辑代数译码方法研究
15.
Construction of Quasi-Cyclic LDPC Block and Convolutional Codes
准循环LDPC分组码和卷积码的构造
16.
Packet decoding method for convolutional codes based on FPGA
基于FPGA的卷积码分组译码方法
17.
A High-speed viterbi-decoding Scheme for Convolutional Code
卷积码的Viterbi高速译码方案
18.
Decoder Design for Convolutional Code Based on Viterbi Method
基于维特比算法的卷积码译码器设计