1.
A Partly-parallel Coder Structure of Quasi-cyclic Low-density Parity-check Codes
一种准循环低密度校验码部分并行编码结构设计
2.
"because most of the 20 amino acids are coded for by more than one codon, the code is called degenerate."
由于在20种氨基酸中,大部分藉由一种以上的密码子进行编码,这种编码称作简并密码。
3.
A separate parallel MQ coder and its VLSI architecture
分步式并行MQ编码及其VLSI设计
4.
The Coding System Based on the Partly Meaning and Feature Attributes;
基于部分赋义加特征属性的编码体系——浅析钢铁行业编码解决方案
5.
The control system processes the subcode that is encoded on the CD.
控制系统处理编码于CD中的子码部分。
6.
Four different kinds of texel block partition methods and corresponding coding algorithms are adapted according to the local spectrum feature of the texture image.
针对纹理图象的局部特征，采用4种不同的纹理单元划分和编码算法来对其进行编码。
7.
The Analysis and Research of Shipbuilding Coding System Based on Concurrent Engineering Model;
基于并行工程模式的船舶建造编码系统的分析与研究
8.
The CODEC can be used to carry on coding transmission and decoding reception in parallel with code error detection and bit synchronized signal recovering.
该编译码器能进行并行发送编码和接收译码,并带有误码检测和位同步提取的功能。
9.
a two-part code assigned to banks and savings associations; the first part shows the location and the second identifies the bank itself.
指定给银行和存款协会的由两部分组成的编码；第一部分表明位置，第二部分代表银行自身。
10.
Parallel Algorithm Design and Optimization for H.264 Video Encoding;
H.264并行编码算法的研究和优化
11.
FPGA Implementation of a Novel Parallel Turbo Encoder/Decoder;
一种新型并行Turbo编译码器的FPGA实现
12.
Research on FPGA Implementation of a Multi-bit-plane Parallel Algorithm for Image Coding;
位平面并行的CCSDS编码研究及其FPGA实现
13.
An Achievement on FPGA of CRC-16 Encoder with 32 Bits Parallel Data;
32位并行数据的CRC-16编码器的FPGA实现
14.
The H.264 Video Parallel Codec Based on GPU
基于GPU的H.264视频并行编解码器
15.
VLSI Architecture of Multi-bit Parallel MQ Coder
多位并行MQ编码的VLSI结构研究
16.
Study and Implementation of AVS Encoding Algorithm Based on Slice Parallel
AVS编码器Slice并行处理算法研究与实现
17.
A parallel architecture design of CAVLC encoder in H.264
H.264中并行化的CAVLC编码器架构设计
18.
A CABAC Parallel Encoding Method for Multithreading
基于多线程的CABAC并行编码方法