1.
Method of Clock Phase Correction in Wide-band Data Acquisition Based on FPGA
基于FPGA的宽带数据采集时钟相位校正方法
2.
the position of the hands on the clock.
时钟上指针摆放的位置
3.
single-phase clock generator
单相时钟脉冲发生器
4.
Switched capacitor( SC) unit delayer, positive negative proportors and adder were designed using two phase clocks.
用二相时钟设计了对寄生电容低灵敏的开关电容单位延时器、负比例器和加法器.
5.
Interval is either not on a 15 minute boundary or does not divide a day evenly. The interval will be adjusted accordingly.%0
间隔既不是严格以 15 分钟为单位，也不是将一天的时间平分，而是相应地进行调整。%0
6.
Their inner clocks tell them just where the Sun will be and they change their course correspondingly
它们体内的时钟告诉他们太阳应在的位置，据此它们相应地改变前进的方向。
7.
The ADC aperture jitter must be minimal, and the sampling clock generated from a low phase-noise quartz crystal oscillator.
ADC的孔径抖动必需尽可能的小，而且要使用低相位噪声的石英晶体振荡器作为采样时钟发生器。
8.
But compared to the SAR, the Chinese mainland's lovers were the seventh most lengthy in the world on20 minutes.
但与香港相比，中国大陆伴侣的性生活时间则以20分钟位居世界第七。
9.
The cardinal point on the mariner's compass90=clockwise from due north and directly opposite west.
东方航海罗盘上一个基本方位，正北方向顺时钟转90°或指正西的相反方向
10.
Pls insert the rest time u want(unit:min)
请输入您打算休息的时间（单位：分钟）
11.
Changes date, time, location and alarm settings.
修改日期、时间、位置和闹钟设置。
12.
Research of Time-synchronization and Localization in Underwater Wirelss Sensor Networks
水下传感网时钟同步与节点定位研究
13.
Design of DPLL for Bit Synchronous Clock Based on FPGA
基于FPGA的提取位同步时钟DPLL设计
14.
The sound In line with the time
按照时间，钟声响相应的次数
15.
in the direction opposite to the rotation of the hands of a clock.
与时钟指针的旋转方向相反。
16.
One man and one woman meet and talk for seven minutes.
一男一女相见并有7分钟的谈话时间，
17.
exposure of a film for a relatively long time (more than half a second).
胶卷曝光时间相对较长（超过半秒钟）。
18.
The method of observation resembles the stopwatch reference to a clock.
观测方法跟停表时钟法相似。