1.
Design and implementation of a full parallel LDPC decoder
LDPC码全并行译码器的设计与实现
2.
Design and Realization of Improved All-parallel Viterbi Decoder
改进型全并行Viterbi译码器设计与实现
3.
Design and Implementation of Hign Throughput Parallel Turbo Decoder;
高速并行Turbo译码器的设计与实现
4.
FPGA Implementation of a Novel Parallel Turbo Encoder/Decoder;
一种新型并行Turbo编译码器的FPGA实现
5.
Design and Implementation of Configurable Parallet BCH Decoder
可配置并行BCH译码器的设计与实现
6.
High-Speed Parallel BCH Decoder Circuit in VLSI
高速并行BCH译码器的VLSI设计
7.
The CODEC can be used to carry on coding transmission and decoding reception in parallel with code error detection and bit synchronized signal recovering.
该编译码器能进行并行发送编码和接收译码,并带有误码检测和位同步提取的功能。
8.
Parallel complementary decoding based on OSD and Chase
OSD和Chase的并行互补译码
9.
Research on Construction, Parallel Concatenation and Decoder Design of Low-Density Parity-Check Codes;
低密度奇偶校验码构造、并行级联与译码器设计的研究
10.
Parallel Maximum Likelihood Decoding Algorithm for RM Codes
RM码的一种并行最大似然译码算法
11.
Decoding Structure of Turbo Code Based on Parallel Prediction Control
基于并行预测控制的Turbo码译码结构
12.
The interpretation is carried out by the instruction decoder.
该翻译借指令译码器来进行。
13.
A cross-compiler runs on a host computer and produces object code for the target.
交叉编译器在主机上运行并且产生目标机的目标代码。
14.
Parallel Processing Design for LTE PUSCH Channel Demodulation and Decoding Based on Multi-Core Processor
基于多核处理器架构的LTE PUSCH信道解调译码并行处理设计
15.
This paper is mainly about a kind of pre-revising Manchester decoder for computer serial bus communications.
文章针对计算机系统中串行总线的通讯，提出并实现了一种预测校正型曼Ⅱ码译码器。
16.
Superposition feedback decoding algorithm for parallel concatenated block code based on correlation operation
并行级联分组码基于相关运算的叠加反馈译码
17.
A New Iterative Decoding Algorithm of Parallel Concatenated Block Code
并行级联分组码的一种新的迭代译码算法
18.
The book was translated into many versions and sold all over the world.
这本书被译成多种译本并行销全球。