1.
Design of 2.5GHz Full Speed Clock and Data Recovery Circuit
2.5GHz全速率时钟数据恢复电路的设计
2.
Design and Implementation of a 2.5Gbps Clock Data Recovery Circuit for PCI Express;
PCI Express中的2.5Gbps时钟数据恢复电路的设计与实现
3.
Design and Implementation of a High Performance Clock and Date Recovery Circuit
高性能时钟数据恢复电路的设计与实现
4.
Design of high-speed clock and data recovery circuit Based on FPGA
基于FPGA的高速时钟数据恢复电路的实现
5.
Design and implementation of a 54Mb/s NRZ clock data recovery circuit
54Mb/s NRZ时钟数据恢复电路的设计与实现
6.
A 1.25Gb/s Clock and Data Recovery Circuit Used in Gigabit Ethernet;
用于1.25Gb/s千兆以太网的时钟数据恢复电路的设计
7.
Design and Implementation of a 2.5Gbps Clock Data Recovery Circuit for PCI Express
应用于PCI-Express的2.5Gbps时钟数据恢复电路的设计与实现
8.
Design of Phase-locked Loop for USB2.0 Application;
应用于USB2.0时钟数据恢复的锁相环设计
9.
The Design and Realization of Clock and Data Recovery of Burst Mode
突发模式时钟数据恢复的研究与实现
10.
Research and Design of High Speed Clock Recovery Circuit on ASIC
高速时钟恢复电路的ASIC研究与设计
11.
A clock and data recovery method based on phase detector implemented by delay chain in FPGA
利用FPGA延时链实现鉴相器时钟数据恢复
12.
Research on Ultra High Speed Clock Recovery IC for Optical-Fiber Transmission System;
光纤传输系统用超高速时钟恢复集成电路研究
13.
Design of 2.5 GB/s Clock Recovery Circuit Based on 0.18 μm CMOS Technique
基于0.18μm CMOS工艺的2.5GB/s时钟恢复电路设计
14.
Design of a High-speed Integrated PLL for Clock Recovery Circuit
用于时钟恢复电路的高速集成锁相环设计研究
15.
Research on Clock Feeds and Recovery Methods in Railway TV SFN System
铁路电视SFN系统时钟馈送和恢复方法技术研究
16.
System clock recover is the key in digital TV system.
系统时钟恢复是数字电视系统设计中的难点。
17.
The Data and Clock lines are both open collector.
数据和时钟线都是集电极开路的。
18.
The Integrate Circuit Design for 10-40Gb/s Optical Communication and 10 Gigabit Ethernet Clock-Recovery;
10-40Gb/s光通信与万兆以太网时钟恢复电路芯片研究