1.
Design and Implementation of Configurable Parallet BCH Decoder
可配置并行BCH译码器的设计与实现
2.
High-Speed Parallel BCH Decoder Circuit in VLSI
高速并行BCH译码器的VLSI设计
3.
Realization of the Encoder of BCH(23,12) Code Based on FPGA;
基于FPGA的BCH(23,12)码编译码器的实现
4.
Research and FPGA Implementation of BCH Encoder and Decoder in Digital Television Broadcasting System;
数字电视传输系统中BCH码编/译码器的研究与FPGA实现
5.
The Optimization and Application of Decoding Algorithm of Binary BCH Code;
二元BCH码译码算法的优化与应用
6.
A Coding and Decoding Algorithm and its implementation of shortened BCH Codes(16,8,5)
缩短BCH码(16,8,5)编译码算法及其实现
7.
The Implementation of BCH Hardware Decoder on BM Algorithm
基于BM算法的BCH码的译码硬件实现
8.
The change bit one-by-one decode method for BCH and its application in GPON system
BCH码逐位取反译码方法及其在GPON系统中的应用
9.
Parametric Design of BCH/RS Coder/Decoder;
参数化的BCH/RS编解码器设计
10.
Bose-Chaudhuri-HocQuenghem code
错误纠正码，bch 码
11.
An area-efficient parallel BCH decoder supporting foresighted error search
一种支持预搜索的面积紧凑型BCH并行译码电路
12.
SLC/MLC NAND FLASH Controller VLSI Design with BCH Encoder and Decoder
一种含BCH编解码器的SLC/MLC NAND FLASH控制器的VLSI设计
13.
One Method to Solve the BCH Code Error-locator Equation Suitable for Implementation in Semiconductor Memories
一种适于半导体存储器的BCH码错误定位方程求解方法
14.
Christmas tree type decoder
“圣诞树”型译码器
15.
FPGA Implementation of SOVA-Based Turbo Decoder;
Turbo码SOVA译码器FPGA实现
16.
The New Exact Value of (k,r)-arcs and Acceleration of the Decoding Procedure of BCH Code;
（k，r）-arcs新精确值和BCH码解码的加速
17.
A Study on BCH Codes Based on the Group Change in the VWDK System
基于群变换的BCH码在VWDK系统中的研究
18.
Design and implementation of a high-throughput decoder for multi-rate LDPC code
多码率LDPC码高速译码器的设计与实现