1.
Design and Realization of a Mixed-Signal PLL in 0.13μm CMOS Process;
一款0.13微米工艺下数模混合锁相环的设计与实现
2.
Design of 400MHz～950MHz PLL for Communication and Math Modeling;
通讯用400MHz～950MHz锁相环设计及数学建模
3.
Modeling, Design and Implementation of Phase-locked Loop Frequency Synthesizer;
锁相环频率合成器建模、设计与实现
4.
Research on All Digital Phase-Locked Loop with High Precision Automatic Modulus Control;
高精度自动变模控制全数字锁相环的研究
5.
Automatic Modulus Controlled All Digital Phase Locked Loop with Large Lock-in Range
一种自动变模控制的宽频带全数字锁相环
6.
A Novel All-digital Phase-locked Loop Z-domain Model in Time Domain
一种新型的时间域全数字锁相环Z域模型
7.
Digital Tuning System of Color TV PLL Frequency Synthesis
锁相环频率合成方式的彩电数字调谐系统
8.
Behavior Modeling of PLL and Its Application in Video Horizontal PLL
锁相环行为级建模及在视频行锁相中的应用
9.
The Study on Performance of Phase-Locked Loop Based on Mode-Locked Fiber Laser;
基于锁模光纤激光器的锁相环特性的研究
10.
Estimate of Longitudinal Data Mixed-effect Model Based on Correlation Data;
基于相关数据下的纵向数据混合效应模型估计
11.
A True Random Number Generator Based on PLL
一种基于锁相环的真随机数发生器
12.
Research and Design of All-digital PLL with High Frequency and Low Jitter Performance;
高速低抖动全数字锁相环的设计研究
13.
Design of Phase-locked Loop for USB2.0 Application;
应用于USB2.0时钟数据恢复的锁相环设计
14.
The Design of Digital Circuits in CMOS Charge-Pump Phase-Locked Loop;
CMOS电荷泵锁相环中的数字电路设计
15.
APPLICATION OF ISPLSI1016 IN DIGITAL PHASE-LOCKED LOOP;
ispLSI1016在数字锁相环中的应用
16.
Detetion of Harmonic Waves Based on DPLL Synchronous Sampling
基于数字锁相环同步采样的谐波检测
17.
Design of Digital Phase Locked Loop Used in SDH Equipment Clock
SDH设备时钟中的数字锁相环设计
18.
The Implementation and Analysis of Digital Phase-locked Loop Based on FPGA
基于FPGA的数字锁相环实现与性能分析