1.
Optimized implementation scheme of three phase phase-locked loop based on FPGA
基于FPGA的三相锁相环的优化设计方案
2.
Design and Realization of Phase Locked Loop under Three-phase Unbalance Voltages
三相电压不平衡条件下锁相环的设计与实现
3.
An improved method without PLL on harmonics detection
一种改进的无锁相环三相电路谐波电流检测方法
4.
Behavior Modeling of PLL and Its Application in Video Horizontal PLL
锁相环行为级建模及在视频行锁相中的应用
5.
Single-phase Phase-Locked Loop based on Modified Instantaneous Reactive Power Theory
基于改进瞬时无功理论的单相锁相环
6.
The Phase Locking Trigger Controller for 3-Ф FB Circuit with Thyristor
晶闸管三相全桥电路锁相触发控制器
7.
Relationship Analysis between PLL Phase Noise and PLL Bandwidth
锁相环相位噪声与环路带宽的关系分析
8.
PLL lock time is below 15us,power dissipation is below 10mw.
该锁相环的锁定时间低于 15us,功耗小于 10mW。
9.
The Study on Performance of Phase-Locked Loop Based on Mode-Locked Fiber Laser;
基于锁模光纤激光器的锁相环特性的研究
10.
Analysis of the Magnitude Frequency Responses of Software Phase-Locked Loop and Its Loop Filter
软件锁相环环路滤波器和闭环幅频响应分析
11.
Special PLL used in target RF simulation of the radio detonator
引信目标射频仿真中的特殊锁相环路
12.
A True Random Number Generator Based on PLL
一种基于锁相环的真随机数发生器
13.
A Fast Acquisition PLL with Wide Tuning Range
一种快捕获宽调节范围的锁相环(英文)
14.
Modeling, Design and Implementation of Phase-locked Loop Frequency Synthesizer;
锁相环频率合成器建模、设计与实现
15.
Modeling and Design of Charge Pump Phase-Locked Loops;
电荷泵锁相环的模型研究和电路设计
16.
Design of Fully Integrated Phase-Locked Loop for GPS Receiver;
用于GPS接收机的全集成锁相环设计
17.
Design of Novel Fully-differential Charge Pump for PLL;
锁相环用新型全差分CMOS电荷泵设计
18.
Research and Design of All-digital PLL with High Frequency and Low Jitter Performance;
高速低抖动全数字锁相环的设计研究