1.
Research on Configurable Turbo Decoder in Wireless Channel
无线信道可配置Turbo译码组件技术研究
2.
Study and FPGA Implementation of MIMO Detection with Variable Parameter
可配置MIMO译码组件的FPGA实现
3.
The Software Realization of Shortened Cycle Code(26,16) Encoding and Decoding
缩短循环码(26,16)编码和译码的软件实现
4.
Research on BTC s Chase Decoding Algorithm;
分组Turbo码的Chase译码算法研究
5.
Studies on Space-Time Block Coding & Decoding Algorithms and Application;
空时分组码的编译码算法及应用研究
6.
Packet decoding method for convolutional codes based on FPGA
基于FPGA的卷积码分组译码方法
7.
An improved decoding algorithm for block Turbo codes
一种改进的分组Turbo码译码算法
8.
The Decoding Research and Hardware Implementation of LDPC Codes Based on FPGA;
基于FPGA的LDPC码译码研究与硬件实现
9.
The Research of Turbo Code and Hardware Design;
Turbo码编译码研究及其硬件设计
10.
Principles of the Codec for LDPC Codes and Its Hardware Implementation;
LDPC码编译码器的原理及其硬件实现
11.
The Hardware Design of Concatenated Decoder Based on FPGA
基于FPGA的级联码的译码器的硬件设计
12.
Research on the Implementation of CCSDS-RS(255,223) High Speed Decoder
CCSDS-RS(255,223)码高速译码器的硬件实现研究
13.
The Implementation of BCH Hardware Decoder on BM Algorithm
基于BM算法的BCH码的译码硬件实现
14.
Research on the Decoding of Linear Codes over Rings with Lee Metric;
环上线性分组码基于Lee度量译码的研究
15.
Studies on Space-Time Block Code Based on Rotating Constellations Coding & Decoding Algorithms;
基于星座旋转的分组空时码编译码算法研究
16.
The Design and the Realization of STBC Coder and Decoder Based on DSP;
基于DSP的空时分组码编译码器的设计与实现
17.
Decoding Algorithm for Block Turbo Codes Based on the Adaptive Quantized Testing Sequences
自适应量化测试序列数的分组Turbo码译码算法
18.
Superposition feedback decoding algorithm for parallel concatenated block code based on correlation operation
并行级联分组码基于相关运算的叠加反馈译码