1.
Study of Fractional-N Digital Phase Locked Loop Frequency Synthesizer;
分数分频数字锁相频率合成器的研究
2.
Research on Adpll-Basedtime Digital Converter
基于全数字锁相环的时间数字转换器的研究
3.
Research and Design of All-digital PLL with High Frequency and Low Jitter Performance;
高速低抖动全数字锁相环的设计研究
4.
Embedded Digital Lock-in Amplifier Based on TMS320C6701EVM;
基于TMS320C6701EVM的嵌入式数字锁定放大器
5.
Design of Digital Phase locked Frequency Synthesize Based on TC9181;
基于TC9181的数字锁相频率合成器的设计
6.
APPLICATION OF ISPLSI1016 IN DIGITAL PHASE-LOCKED LOOP;
ispLSI1016在数字锁相环中的应用
7.
Detetion of Harmonic Waves Based on DPLL Synchronous Sampling
基于数字锁相环同步采样的谐波检测
8.
Design of Digital Phase Locked Loop Used in SDH Equipment Clock
SDH设备时钟中的数字锁相环设计
9.
The Implementation and Analysis of Digital Phase-locked Loop Based on FPGA
基于FPGA的数字锁相环实现与性能分析
10.
Design of all digital phase locked loop based on FPGA
基于FPGA的全数字锁相环的设计
11.
Design of Frequency Scanner Based on Delta-Sigma Fractional-N PLL LMX2471
基于小数分频数字锁相环LMX2471的扫频仪设计
12.
The Research on Indirect Frequency Synthesizer of Low Phase Noise Digit PLL
低相噪数字锁相间接频率合成器的研究
13.
Research on All Digital Phase-Locked Loop with High Precision Automatic Modulus Control;
高精度自动变模控制全数字锁相环的研究
14.
Design of Temperature Frequency Conversion Circuit Based on Digital Phase Locked Loop;
基于数字锁相环的温控变频电路的设计
15.
sequence of numbers or letters used to open a combination lock
（用以开启暗码锁的）数字或字母组合.
16.
a sequence of numbers or letters that opens a combination lock.
一串能打开号码锁的数字或字母。
17.
"Unable to unlock a range of bytes for
"无法解除“%1”字节数范围的锁定。\
18.
The Design of Digital Circuits in CMOS Charge-Pump Phase-Locked Loop;
CMOS电荷泵锁相环中的数字电路设计