1.
Analysis and Design of Low-Jitter Clock Driver for Wideband ADC
宽带ADC低抖动时钟驱动电路的分析与设计
2.
Design of Low-Clock Jitter VCO with Strong Ability of Rejecting Power Supply Noise
高抗电源噪声的低时钟抖动VCO设计
3.
The sampling clock generator must also have adequate spectral purity.
时钟发生电路固有的抖动应该足够小。
4.
The ADC aperture jitter must be minimal, and the sampling clock generated from a low phase-noise quartz crystal oscillator.
ADC的孔径抖动必需尽可能的小，而且要使用低相位噪声的石英晶体振荡器作为采样时钟发生器。
5.
Figure 5.36 shows the relationship between sampling clock jitter and SNR previously presented.
图5.36显示了采样时钟抖动和信噪比之间的关系。
6.
Research on the Clock Jitter Effects on the Performance of GPS Tracking
采样时钟抖动对GPS信号跟踪性能影响研究
7.
Design of SDH/SONET Tributary Clock Jitter Attenuation Digital Phase Lock Loop
SDH/SONET支路时钟抖动衰减数字锁相环设计
8.
"Pulse front edge jitter (firing-time jitter, pulse starting-time jitter)"
脉冲前沿抖动(点火时间抖动、脉冲起始时间抖动)
9.
Analysis of clock jitter error in digital-to-analog converter based on Linear Frequency Modulated Signal
基于线性调频信号的数模转换器时钟抖动误差分析
10.
Error analysis on numerical double integration in acceleration measurement with clock jitter
时钟抖动下加速度测量值的数值双积分误差(英文)
11.
pronounce with a trill, of the phoneme .
发音素r时用抖动发出。
12.
Curiously, the chiming of the hour seemed to have put new heart into him.
怪得很，这报时的钟声仿佛让他抖擞了精神。
13.
Her voice was low and shaky with emotion.
她的声音低沉，因激动而有些颤抖。
14.
Research and Design of All-digital PLL with High Frequency and Low Jitter Performance;
高速低抖动全数字锁相环的设计研究
15.
Low Jitter Design for 1.25 Gbps SerDes Receiver
1.25Gbps串并并串转换接收器的低抖动设计
16.
High voltage low jitter Marx generator of prototype module of primary test stand
Z箍缩实验装置高压低抖动Marx发生器
17.
Then, indeed, Mr. Dimmesdale shuddered, and slightly stirred.
此时，丁梅斯代尔先生确实抖了抖，微微一动。
18.
The main features of this tremor are its low frequency, irregular rhythm, presence at rest, and acceleration during posture and active movement.
其特征主要为低频率的颤抖出现在静止状态、肌肉收缩生成动作时以及维持固定姿势时。