1.
Because of its main body is realized by software, it is convenient to add acquisition function to the DDL.
由于采用软件来实现同步，还可方便地将捕获功能加入锁定环路当中。
2.
A New Mixed-mode Design of DCM Clock Delay Locked Loop
一种新型混合信号时钟延时锁定环电路设计
3.
Cannot perform locking operation because the locking file path was not found.
无法执行锁定操作，因为没有找到锁定文件路径。
4.
Analysis of the Magnitude Frequency Responses of Software Phase-Locked Loop and Its Loop Filter
软件锁相环环路滤波器和闭环幅频响应分析
5.
NOTE: SEE FI1 TO DETERMINE WHICH DOOR LOCK CIRCUIT IS SHORTE
注意：见图１确定电路短路的门锁。
6.
PLL lock time is below 15us,power dissipation is below 10mw.
该锁相环的锁定时间低于 15us,功耗小于 10mW。
7.
A Lock-in Effect Analysis and Lock-out Path of Regional Economic Development Imbalance in Guangdong;
广东区域发展不平衡的锁定效应与解锁路径
8.
Special PLL used in target RF simulation of the radio detonator
引信目标射频仿真中的特殊锁相环路
9.
Modeling and Design of Charge Pump Phase-Locked Loops;
电荷泵锁相环的模型研究和电路设计
10.
The Design of Digital Circuits in CMOS Charge-Pump Phase-Locked Loop;
CMOS电荷泵锁相环中的数字电路设计
11.
The Improvement of Thyristor Power Supply Device Based on Synchronous Circuit of Phase Locked Loop and Frequency Multiplier;
基于锁相环倍频同步电路的电源改进
12.
THE DESIGN AND STNDY OF THE CAI COURSEWARE OF“PHASE LOCKED LOOP”THEORY;
《锁相环路原理》CAI课件的设计与研制
13.
THE DESIGN AND THE SPECIALITY OF PHASE LOCKED LOOP THEORY COMPUTER ASSISTED INSTRUCTION SOFTWARE;
《锁相环路原理》CAI课件的设计与特点
14.
The Integrated Circuits of NE564 Phase-locked loop Principle and Application
锁相环集成电路NE564原理及应用
15.
A Fast Acquisition PLL with Tunable Loop Bandwidth
一种快速捕获、带宽可调的锁相环电路
16.
An Improved CMOS PLL with Dual Control Paths
一种改进的双控制通路锁相环(英文)
17.
Cycle-deadlock Control of Rail Guided Vehicles Systems via Petri Nets
基于Petri网的RGVs系统中环路死锁研究
18.
Design of Fourth-Order PLL Synthesizer
一种四阶锁相频率合成器的环路设计